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Initial commit of the Verilog DV style guide
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Signed-off-by: Udi Jonnalagadda <udij@google.com>
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Udi Jonnalagadda committed Feb 11, 2020
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Expand Up @@ -4,6 +4,7 @@ This repository contains style guides curated by lowRISC for use in our
code and documentation.

- [SystemVerilog style guide](VerilogCodingStyle.md)
- [SystemVerilog style guide for DV](VerilogForVerificationStyle.md)

We invite issues and pull requests to add clarity to these guides.

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