[rv_timer]: issues found by running CSR test suite

[sriyerg]

1: intr_state0 timer status is set right out of reset

In timer_core, the intr_state0 is set right out of reset without any timer configuration. In the timer reg hjson file, intr_state0 reset value is indicated as 0 - but the rtl is reading back 1, causing the test to fail.

On further inspection, looks like timer_core generates interrupt signal when mtime >= mtimecomp, both of which are 0 right out of reset. This results in intr_state0 to be set.

Is this an expected behavior? If yes, then please advise how to proceed - either exclude this register from reset value check, or fix the reg hjson to indicate the reset value of 1.

[sriyerg]

2. intr_test0 is marked as "RW" but but reads all 0s

[mdhayter]

Should mtimecmp reset to all ones? This would be consistent with all the code examples being careful to only have intermediate states in the future compared to the time being set for interrupt?

[eunchan]

Makes sense. I will revise the design to reset mtimecmp to '1. I remember we had a discussion that `mtimecmp` shouldn't be reset by the main reset (but only with POR?) I cannot find the thread. Does anyone remember?

…

On Jun 1, 2019, at 5:10 AM, mdhayter ***@***.***> wrote: Should mtimecmp reset to all ones? This would be consistent with all the code examples being careful to only have intermediate states in the future compared to the time being set for interrupt? — You are receiving this because you were assigned. Reply to this email directly, view it on GitHub <#48?email_source=notifications&email_token=AAJDG3WSVMW6J6XYYLSPFZ3PYJRL7A5CNFSM4HR6XKE2YY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGODWW7JVA#issuecomment-497939668>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AAJDG3WDEUIZSVDVNGHQYUTPYJRL7ANCNFSM4HR6XKEQ>.

[imphil]

I remember we had a discussion that mtimecmp shouldn't be reset by the main reset (but only with POR?) I cannot find the thread. Does anyone remember?

I don't remember this discussion, but maybe @tjaychen can help out, he has looked at resets recently.

@eunchan Do you think you can you get this done by the end of the week? (I see you already have a patch in your tree?) No worries otherwise, it's not critical.

(Motivation: We have a TODO with this issue number in ./hw/ip/rv_timer/dv/env/seq_lib/rv_timer_csr_vseq.sv, we need to either rewrite it or remove it before the repo move.)

[sjgitty]

@eunchan is this done at this time? @shakushw

[shakushw]

@eunchan is this done at this time? @shakushw

Issues reported are resolved with the current rv_timer rtl.
@eunchan please let me know if i close this issue.

[eunchan]

I will close. Thanks