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Programming exercise: Fix an issue with VHDL not showing build failed correctly #8945

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merged 7 commits into from
Jul 5, 2024

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@BBesrour BBesrour commented Jul 2, 2024

Checklist

General

Motivation and Context

Fix issue: #8886

Description

The problem is due to our VHDL template, not localci. The template generates a result.xml even though the code did not build, which makes artemis think that tests were run, so code was built. I adjusted the template so that it doesn't generate a test when build fails

I changed the template we use so that it is more inline with the other programming languages. Now, we generate result.xml only if the code compiles and the testbench was run. We generate the testcases using the python script using the output of the testbench.
The new template should serve as a guide for instructors on how to generate test cases for vhdl exercises

This solution, however, introduces another small issue. When the instructor creates the exercise, the template result will not show the failed tests since it doesn't compile
image

Steps for Testing

Prerequisites:

  • 1 Student
  • 1 exam with a vhdl programming exercise with test cases visibility set to After due date (default setting)
  1. open exercise as student
  2. submit code (without changing anything), result has to be: 0%, Build failed
  3. Copy solution code from the solution repository (only verzoegerung.vhd is necessary)
  4. Submit code -> result has to be: 0%, Build successful, no tests executed

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Review Progress

Code Review

  • Code Review 1
  • Code Review 2

Manual Tests

  • Test 1
  • Test 2

Summary by CodeRabbit

  • Bug Fixes

    • Enhanced the compileTest.py script to handle test failures more efficiently by returning early when errors occur.
  • New Features

    • Added comprehensive test cases and assertions to various VHDL testbenches to validate the behavior under different conditions.
    • Introduced new commands in VHDL Makefiles to elaborate and run testbenches, improving the build and test process.
  • Improvements

    • Renamed functions and updated file operations to streamline VHDL file handling and preparation in scripts.
    • Enhanced commenting and organization in VHDL testbenches for better readability and maintenance.

@BBesrour BBesrour self-assigned this Jul 2, 2024
@BBesrour BBesrour requested a review from a team as a code owner July 2, 2024 12:13
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coderabbitai bot commented Jul 2, 2024

Walkthrough

This update primarily enhances the VHDL test environment by renaming and modifying functions in default.sh to better manage testbench files, expanding Makefile commands to handle testbench elaboration and execution, and refining VHDL testbench and solution files with improved processes, detailed test cases, and assertions. The compileTest.py script is adjusted for consistent handling of test result logging.

Changes

Files Change Summary
src/.../vhdl/default.sh Renamed function prepare_makefile to prepare_files, removed obsolete file operations, and modified copying of testbench files.
src/.../vhdl/exercise/Makefile, src/.../vhdl/solution/Makefile, src/.../test/Makefile Added commands for elaborating and running VHDL testbenches in the all target.
src/.../vhdl/exercise/verzoegerung_tb.vhd, src/.../vhdl/solution/verzoegerung_tb.vhd, src/.../vhdl/test/verzoegerung_tb.vhd Enhanced testbench with improved clock generation, stimulus processes, and detailed test cases with assertions.
src/.../vhdl/solution/verzoegerung.vhd Adjusted control flow and added comments for handling synchronous reset.
src/.../test/compileTest.py Changed export_junit function to return early on failure without adding failure information and added newline at file end.

Sequence Diagram(s)

sequenceDiagram
    participant User
    participant Script as default.sh
    participant AssignmentDir as assignment Directory
    participant Tests as tests Directory

    User->>Script: Execute prepare_files()
    Script->>AssignmentDir: Remove _tb.vhd files
    Script->>Tests: Copy *_tb.vhd files to assignment/
    Script->>AssignmentDir: Place copied *_tb.vhd files

    User->>Makefile: Run all target
    Makefile->>GHDL: Elaborate $(NAME)_tb
    Makefile->>GHDL: Run $(NAME)_tb
Loading
sequenceDiagram
    participant User
    participant CompileTest as compileTest.py
    participant GHDL
    participant Result as Test Result
    
    User->>CompileTest: Run export_junit()
    CompileTest->>GHDL: Execute VHDL Testbench
    GHDL->>CompileTest: Return stdout, stderr, retCode
    alt retCode = 0
        CompileTest->>Result: Add success info
    else retCode != 0
        CompileTest->>CompileTest: Return early
    end
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Recent review details

Configuration used: .coderabbit.yaml
Review profile: ASSERTIVE

Commits

Files that changed from the base of the PR and between 14f5292 and bedc3f5.

Files selected for processing (1)
  • src/main/resources/templates/vhdl/test/compileTest.py (2 hunks)
Additional comments not posted (3)
src/main/resources/templates/vhdl/test/compileTest.py (3)

10-10: LGTM!

Returning early when retCode is not equal to 0 prevents the creation of a result.xml file for failed builds, aligning with the PR objective.


43-43: LGTM!

Including stderr in the export_junit call provides more detailed information about the failure, which is useful for debugging.


7-7: Add return type annotation to export_junit.

The function export_junit is missing a return type annotation.

- def export_junit(retCode: int, stdout: str = ""):
+ def export_junit(retCode: int, stdout: str = "") -> None:

Likely invalid or redundant comment.


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@github-actions github-actions bot added server Pull requests that update Java code. (Added Automatically!) template labels Jul 2, 2024
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Actionable comments posted: 5

src/main/resources/templates/vhdl/exercise/Makefile Outdated Show resolved Hide resolved
src/main/resources/templates/aeolus/vhdl/default.sh Outdated Show resolved Hide resolved
src/main/resources/templates/vhdl/solution/Makefile Outdated Show resolved Hide resolved
src/main/resources/templates/vhdl/test/compileTest.py Outdated Show resolved Hide resolved
src/main/resources/templates/vhdl/test/Makefile Outdated Show resolved Hide resolved
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coderabbitai bot previously approved these changes Jul 2, 2024
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@Strohgelaender Strohgelaender left a comment

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code

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@marlon-luca-bu marlon-luca-bu left a comment

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Code

@krusche krusche changed the title Programming exercise: Fix build failed not show Programming exercise: Fix an issue with VHDL not showing build failed correctly Jul 5, 2024
@krusche krusche added this to the 7.4.1 milestone Jul 5, 2024
@krusche krusche merged commit eab9f6c into develop Jul 5, 2024
26 of 28 checks passed
@krusche krusche deleted the bugfix/general/fix-build-failed-not-show branch July 5, 2024 20:08
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