Sayma RTM: hold hmc7043 in reset/mute state during init.

[hartytp]

Tested on my Sayma. Since implementing this fix, I haven't seen any more runtime crashes (although, serwb still seems unreliable on my board).

This requires the HMC7043 RESET line to be connected in hardware. My board had been reworked to short this to GND. NB connecting the HMC7043 RESET line breaks the Si5324 because they share a reset line.

[sbourdeauducq]

Remove the empty line.

[sbourdeauducq]

Why not use the GPIO out core instead of adding this to the CRG? CRG is normally used to clock the local design only.

[hartytp]

Lack of familiarity with misoc/to the man with a hammer everything is a nail.

[hartytp]

Do you mind changing this when merging?

[sbourdeauducq]

This will need a hardware fix (or at least a review) as well, once the RTM FPGA is loaded by the AMC FPGA.
Maybe add a pull-up on the reset line? Though Xilinx FPGAs sometimes have weak pull-ups when unconfigured (depending on the state of certain pins) so maybe nothing needs to be changed.

[sbourdeauducq]

Indent

[sbourdeauducq]

And there is no time for the HMC7043 to wreak havoc between the release of its reset line and the SPI write that mutes it?

[hartytp]

This will need a hardware fix (or at least a review) as well, once the RTM FPGA is loaded by the AMC FPGA.
Maybe add a pull-up on the reset line?

hmmm...yes. That's a good idea. Let's do that.

[hartytp]

And there is no time for the HMC7043 to wreak havoc between the release of its reset line and the SPI write that mutes it?

Yes, there is. Although I haven't looked on a scope yet to see if this causes problems in practice (that's next on my to do list).

I think that for the next version of Sayma it would be wise to consider adding FETs that can be used to shut down the HMC7043 outputs by cutting off the biasing. I believe that this PR represents the best we can do without HW changes.

[gkasprow]

We can add negator that would invert the RESET line. It was foreseen in Sayma rev2

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On 5 June 2018 at 13:23, hartytp ***@***.***> wrote: And there is no time for the HMC7043 to wreak havoc between the release of its reset line and the SPI write that mutes it? Yes, there is. Although I haven't looked on a scope yet to see if this causes problems in practice (that's next on my to do list). I think that for the next version of Sayma it would be wise to consider adding FETs that can be used to shut down the HMC7043 outputs by cutting off the biasing. I believe that this PR represents the best we can do without HW changes. — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#1049 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AEH-vrrmjc6ukyV1rLzOXKpi_ZbYjZ4Rks5t5moggaJpZM4UahZq> .