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Sayma RTM: hold hmc7043 in reset/mute state during init. #1049

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merged 3 commits into from
Jun 5, 2018
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Sayma RTM: hold hmc7043 in reset/mute state during init. #1049

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c31e9de
Sayma RTM: hold hmc7043 in reset/mute state during init.
hartytp Jun 4, 2018
20efc65
Configure HMC7043 to give deterministic phase differences between its…
hartytp Jun 5, 2018
33921ec
Sayma: fix mistake in HMC7043 init code.
hartytp Jun 5, 2018
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40 changes: 26 additions & 14 deletions artiq/firmware/libboard_artiq/hmc830_7043.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -146,6 +146,7 @@ pub mod hmc7043 {
const DAC_CLK_DIV: u32 = 2;
const FPGA_CLK_DIV: u32 = 8;
const SYSREF_DIV: u32 = 128;
const HMC_SYSREF_DIV: u32 = SYSREF_DIV*8; // Must be <= 4MHz

// enabled, divider, analog phase shift, digital phase shift
const OUTPUT_CONFIG: [(bool, u32, u8, u8); 14] = [
Expand Down Expand Up @@ -224,10 +225,17 @@ pub mod hmc7043 {
Ok(())
}

pub fn shutdown() -> Result<(), &'static str> {
pub fn enable() -> Result<(), &'static str> {
info!("enabling hmc7043");

unsafe {
csr::crg::hmc7043_rst_write(0);
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Indent

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And there is no time for the HMC7043 to wreak havoc between the release of its reset line and the SPI write that mutes it?

}

spi_setup();
info!("shutting down");
write(0x1, 0x1); // Sleep mode
write(0x0, 0x1); // Software reset
write(0x0, 0x0); // Normal operation
write(0x1, 0x48); // mute all outputs

Ok(())
}
Expand All @@ -236,11 +244,6 @@ pub mod hmc7043 {
spi_setup();
info!("loading configuration...");

write(0x0, 0x1); // Software reset
write(0x0, 0x0);

write(0x1, 0x40); // Enable high-performace/low-noise mode
write(0x3, 0x10); // Disable SYSREF timer
write(0xA, 0x06); // Disable the REFSYNCIN input
write(0xB, 0x07); // Enable the CLKIN input as LVPECL
write(0x50, 0x1f); // Disable GPO pin
Expand All @@ -254,18 +257,21 @@ pub mod hmc7043 {
(1 << 4) |
(1 << 5));

write(0x5c, (HMC_SYSREF_DIV & 0xff) as u8); // Set SYSREF timer divider
write(0x5d, ((HMC_SYSREF_DIV & 0x0f) >> 8) as u8);

for channel in 0..14 {
let channel_base = 0xc8 + 0x0a*(channel as u16);
let (enabled, divider, aphase, dphase) = OUTPUT_CONFIG[channel];

if enabled {
// Only clock channels need to be high-performance
if (channel % 2) == 0 { write(channel_base, 0x91); }
else { write(channel_base, 0x11); }
if (channel % 2) == 0 { write(channel_base, 0xd1); }
else { write(channel_base, 0x51); }
}
else { write(channel_base, 0x10); }
write(channel_base + 0x1, (divider & 0x0ff) as u8);
write(channel_base + 0x2, ((divider & 0x700) >> 8) as u8);
write(channel_base + 0x1, (divider & 0xff) as u8);
write(channel_base + 0x2, ((divider & 0x0f) >> 8) as u8);
write(channel_base + 0x3, aphase & 0x1f);
write(channel_base + 0x4, dphase & 0x1f);

Expand All @@ -276,6 +282,11 @@ pub mod hmc7043 {
write(channel_base + 0x8, 0x08)
}

write(0x1, 0x4a); // Reset dividers and FSMs
write(0x1, 0x48);
write(0x1, 0xc8); // Synchronize dividers
write(0x1, 0x40); // Unmute, high-performace/low-noise mode

info!(" ...done");

Ok(())
Expand Down Expand Up @@ -305,8 +316,9 @@ pub fn init() -> Result<(), &'static str> {
/* do not use other SPI devices before HMC830 SPI mode selection */
hmc830::select_spi_mode();
hmc830::detect()?;
hmc7043::detect()?;
hmc7043::shutdown()?;
hmc830::init()?;

hmc7043::enable()?;
hmc7043::detect()?;
hmc7043::init()
}
11 changes: 8 additions & 3 deletions artiq/gateware/targets/sayma_rtm.py
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Original file line number Diff line number Diff line change
Expand Up @@ -19,8 +19,11 @@
from artiq import __version__ as artiq_version


class CRG(Module):
class CRG(Module, AutoCSR):
def __init__(self, platform):

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Remove the empty line.

self.hmc7043_rst = CSRStorage(reset=1)

self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
Expand All @@ -31,7 +34,7 @@ def __init__(self, platform):
serwb_refclk_bufr = Signal()
serwb_refclk_bufg = Signal()
self.specials += Instance("BUFR", i_I=self.serwb_refclk, o_O=serwb_refclk_bufr)
self.specials += Instance("BUFG", i_I=serwb_refclk_bufr, o_O=serwb_refclk_bufg)
self.specials += Instance("BUFG", i_I=serwb_refclk_bufr, o_O=serwb_refclk_bufg)

pll_locked = Signal()
pll_fb = Signal()
Expand Down Expand Up @@ -110,6 +113,8 @@ def __init__(self, platform):
csr_devices = []

self.submodules.crg = CRG(platform)
csr_devices.append("crg")
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Why not use the GPIO out core instead of adding this to the CRG? CRG is normally used to clock the local design only.

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Lack of familiarity with misoc/to the man with a hammer everything is a nail.

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Do you mind changing this when merging?


clk_freq = 125e6

self.submodules.rtm_magic = RTMMagic()
Expand Down Expand Up @@ -174,7 +179,7 @@ def __init__(self, platform):
platform.request("ad9154_spi", 0),
platform.request("ad9154_spi", 1)))
csr_devices.append("converter_spi")
self.comb += platform.request("hmc7043_reset").eq(0)
self.comb += platform.request("hmc7043_reset").eq(self.crg.hmc7043_rst.storage)

# AMC/RTM serwb
serwb_pads = platform.request("amc_rtm_serwb")
Expand Down