transport: fix converters/lanes mapping

m-labs · May 12, 2017 · 016ff82 · 016ff82
1 parent 9d20f5e
commit 016ff82
Show file tree

Hide file tree

Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/jesd204b/transport.py b/jesd204b/transport.py
@@ -35,8 +35,8 @@ def __init__(self, jesd_settings, converter_data_width):
         while current_sample < samples_per_clock:
             # frame's samples
             frame_samples = []
-            for i in range(samples_per_frame):
-                for j in range(jesd_settings.nconverters):
+            for j in range(jesd_settings.nconverters):
+                for i in range(samples_per_frame):
                     converter_data = getattr(self.sink, "converter"+str(j))
                     sample = Signal(jesd_settings.phy.n)
                     self.comb += sample.eq(

diff --git a/test/model/transport.py b/test/model/transport.py
@@ -86,8 +86,8 @@ def samples_to_lanes(samples_per_frame, nlanes, nconverters, nbits, samples):
     while n < len(samples[0]):
         # frame's samples
         frame_samples = []
-        for i in range(samples_per_frame):
-            for j in range(nconverters):
+        for j in range(nconverters):
+            for i in range(samples_per_frame):
                 frame_samples.append(samples[j][n+i])
         n += samples_per_frame