elsewhere: do not create interface in default param

migen/bus/csr.py

@@ -18,8 +18,10 @@ class Interconnect(SimpleInterconnect):
 	pass
 
 class Initiator(PureSimulable):
-	def __init__(self, generator, bus=Interface()):
+	def __init__(self, generator, bus=None):
 		self.generator = generator
+		if bus is None:
+			bus = Interface()
 		self.bus = bus
 		self.transaction = None
 		self.done = False
@@ -50,7 +52,7 @@ def _compute_page_bits(nwords):
 		return 0
 
 class SRAM:
-	def __init__(self, mem_or_size, address, bus=Interface()):
+	def __init__(self, mem_or_size, address, bus=None):
 		if isinstance(mem_or_size, Memory):
 			assert(mem_or_size.width <= data_width)
 			self.mem = mem_or_size
@@ -62,6 +64,8 @@ def __init__(self, mem_or_size, address, bus=Interface()):
 			self._page = RegisterField("page", page_bits)
 		else:
 			self._page = None
+		if bus is None:
+			bus = Interface()
 		self.bus = bus
 
 	def get_registers(self):

migen/bus/wishbone.py

@@ -133,8 +133,10 @@ def do_simulation(self, s):
 			self.handler(transaction)
 
 class Initiator(PureSimulable):
-	def __init__(self, generator, bus=Interface()):
+	def __init__(self, generator, bus=None):
 		self.generator = generator
+		if bus is None:
+			bus = Interface()
 		self.bus = bus
 		self.transaction_start = 0
 		self.transaction = None
@@ -178,7 +180,9 @@ def can_ack(self, bus):
 		return True
 
 class Target(PureSimulable):
-	def __init__(self, model, bus=Interface()):
+	def __init__(self, model, bus=None):
+		if bus is None:
+			bus = Interface()
 		self.bus = bus
 		self.model = model
 
@@ -195,12 +199,14 @@ def do_simulation(self, s):
 			bus.ack = 0
 
 class SRAM:
-	def __init__(self, mem_or_size, bus=Interface()):
+	def __init__(self, mem_or_size, bus=None):
 		if isinstance(mem_or_size, Memory):
 			assert(mem_or_size.width <= 32)
 			self.mem = mem_or_size
 		else:
 			self.mem = Memory(32, mem_or_size//4)
+		if bus is None:
+			bus = Interface()
 		self.bus = bus
 
 	def get_fragment(self):