sayma rtm: add clock mezzanine GPIO (#133)

m-labs · Sep 19, 2018 · 4621abc · 4621abc
1 parent ca0df1c
commit 4621abc
Showing 1 changed file with 7 additions and 0 deletions.
diff --git a/migen/build/platforms/sinara/sayma_rtm.py b/migen/build/platforms/sinara/sayma_rtm.py
@@ -123,6 +123,13 @@
         Subsignal("rst_n", Pins("J5")),
         IOStandard("LVCMOS33")
     ),
+
+    ("clk_mez", 0,
+        Subsignal("gpio", Pins("D18 C17 C18 G17"
+                               "F18 H16 G15 G15"
+                               "F15 G14 F14 H17"
+                               "H18 F17 H14 E18")),
+        IOStandard("LVCMOS33")),
 ]