sayma rtm: add clock mezzanine GPIO #133
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| @@ -123,6 +123,13 @@ | |||
| Subsignal("rst_n", Pins("J5")), | |||
| IOStandard("LVCMOS33") | |||
| ), | |||
|
|
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| ("clk_mez", 0, | |||
| Subsignal("gipo", Pins("D18 C17 C18 G17" | |||
hartytp
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