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fix synthesis translate on/off switch

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commit 61b8958953eb062e08a1c6994b255c1f79c57dd8 1 parent 9c7ad6b
Nina Engelhardt authored sbourdeauducq committed
Showing with 2 additions and 2 deletions.
  1. +2 −2 migen/fhdl/verilog.py
4 migen/fhdl/verilog.py
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@@ -169,8 +169,8 @@ def _printcomb(f, ns, display_run):
if f.comb:
# Generate a dummy event to get the simulator
# to run the combinatorial process once at the beginning.
- syn_off = "// synthesis translate off\n"
- syn_on = "// synthesis translate on\n"
+ syn_off = "// synthesis translate_off\n"
+ syn_on = "// synthesis translate_on\n"
dummy_s = Signal(name_override="dummy_s")
r += syn_off
r += "reg " + _printsig(ns, dummy_s) + ";\n"
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