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fix synthesis translate on/off switch

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commit 61b8958953eb062e08a1c6994b255c1f79c57dd8 1 parent 9c7ad6b
authored July 26, 2013 sbourdeauducq committed July 26, 2013

Showing 1 changed file with 2 additions and 2 deletions. Show diff stats Hide diff stats

  1. 4  migen/fhdl/verilog.py
4  migen/fhdl/verilog.py
@@ -169,8 +169,8 @@ def _printcomb(f, ns, display_run):
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 	if f.comb:
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 		# Generate a dummy event to get the simulator
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 		# to run the combinatorial process once at the beginning.
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-		syn_off = "// synthesis translate off\n"
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-		syn_on = "// synthesis translate on\n"
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+		syn_off = "// synthesis translate_off\n"
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+		syn_on = "// synthesis translate_on\n"
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 		dummy_s = Signal(name_override="dummy_s")
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 		r += syn_off
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 		r += "reg " + _printsig(ns, dummy_s) + ";\n"

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