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actorlib/dma_asmi: support for writes

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commit 746e452838036abf22e15763e5f85d1fed1874c4 1 parent e97edd7
Sébastien Bourdeauducq authored
48  examples/dataflow/dma.py
@@ -24,7 +24,7 @@ class MyModelASMI(MyModel, asmibus.TargetModel):
24 24
 
25 25
 def adrgen_gen():
26 26
 	for i in range(10):
27  
-		print("Address:  " + str(i))
  27
+		print("Address:  " + hex(i))
28 28
 		yield Token("address", {"a": i})
29 29
 
30 30
 class SimAdrGen(SimActor):
@@ -36,7 +36,7 @@ def dumper_gen():
36 36
 	while True:
37 37
 		t = Token("data", idle_wait=True)
38 38
 		yield t
39  
-		print("Received: " + str(t.value["d"]))
  39
+		print("Received: " + hex(t.value["d"]))
40 40
 
41 41
 class SimDumper(SimActor):
42 42
 	def __init__(self):
@@ -47,12 +47,12 @@ def trgen_gen():
47 47
 	for i in range(10):
48 48
 		a = i
49 49
 		d = i+10
50  
-		print("Address: " + str(a) + " Data: " + str(d))
  50
+		print("Address: " + hex(a) + " Data: " + hex(d))
51 51
 		yield Token("address_data", {"a": a, "d": d})
52 52
 
53 53
 class SimTrGen(SimActor):
54  
-	def __init__(self):
55  
-		self.address_data = Source([("a", 30), ("d", 32)])
  54
+	def __init__(self, a_nbits):
  55
+		self.address_data = Source([("a", a_nbits), ("d", 32)])
56 56
 		SimActor.__init__(self, trgen_gen())
57 57
 
58 58
 class TBWishbone(Module):
@@ -78,7 +78,7 @@ def do_simulation(self, s):
78 78
 
79 79
 class TBWishboneWriter(TBWishbone):
80 80
 	def __init__(self):
81  
-		self.trgen = SimTrGen()
  81
+		self.trgen = SimTrGen(30)
82 82
 		self.writer = dma_wishbone.Writer()
83 83
 		g = DataFlowGraph()
84 84
 		g.add_connection(self.trgen, self.writer)
@@ -89,28 +89,42 @@ def do_simulation(self, s):
89 89
 		s.interrupt = self.trgen.token_exchanger.done and not s.rd(self.comp.busy)
90 90
 
91 91
 class TBAsmi(Module):
92  
-	def __init__(self, hub):
93  
-		self.submodules.peripheral = asmibus.Target(MyModelASMI(), hub)
94  
-		self.submodules.tap = asmibus.Tap(hub)
95  
-
96  
-class TBAsmiReader(TBAsmi):
97 92
 	def __init__(self, nslots):
98 93
 		self.submodules.hub = asmibus.Hub(32, 32)
99  
-		port = self.hub.get_port(nslots)
  94
+		self.port = self.hub.get_port(nslots)
100 95
 		self.hub.finalize()
  96
+
  97
+		self.submodules.peripheral = asmibus.Target(MyModelASMI(), self.hub)
  98
+		self.submodules.tap = asmibus.Tap(self.hub)
  99
+
  100
+class TBAsmiReader(TBAsmi):
  101
+	def __init__(self, nslots):
  102
+		TBAsmi.__init__(self, nslots)
101 103
 		
102 104
 		self.adrgen = SimAdrGen(32)
103  
-		self.reader = dma_asmi.Reader(port)
  105
+		self.reader = dma_asmi.Reader(self.port)
104 106
 		self.dumper = SimDumper()
105 107
 		g = DataFlowGraph()
106 108
 		g.add_connection(self.adrgen, self.reader)
107 109
 		g.add_connection(self.reader, self.dumper)
108 110
 		self.submodules.comp = CompositeActor(g)
109  
-		TBAsmi.__init__(self, self.hub)
110 111
 
111 112
 	def do_simulation(self, s):
112 113
 		s.interrupt = self.adrgen.token_exchanger.done and not s.rd(self.comp.busy)
113 114
 
  115
+class TBAsmiWriter(TBAsmi):
  116
+	def __init__(self, nslots):
  117
+		TBAsmi.__init__(self, nslots)
  118
+		
  119
+		self.trgen = SimTrGen(32)
  120
+		self.writer = dma_asmi.Writer(self.port)
  121
+		g = DataFlowGraph()
  122
+		g.add_connection(self.trgen, self.writer)
  123
+		self.submodules.comp = CompositeActor(g)
  124
+		
  125
+	def do_simulation(self, s):
  126
+		s.interrupt = self.trgen.token_exchanger.done and not s.rd(self.comp.busy)
  127
+
114 128
 def test_wb_reader():
115 129
 	print("*** Testing Wishbone reader")
116 130
 	Simulator(TBWishboneReader()).run()
@@ -123,7 +137,13 @@ def test_asmi_reader(nslots):
123 137
 	print("*** Testing ASMI reader (nslots={})".format(nslots))
124 138
 	Simulator(TBAsmiReader(nslots)).run()
125 139
 
  140
+def test_asmi_writer(nslots):
  141
+	print("*** Testing ASMI writer (nslots={})".format(nslots))
  142
+	Simulator(TBAsmiWriter(nslots)).run()
  143
+
126 144
 test_wb_reader()
127 145
 test_wb_writer()
128 146
 test_asmi_reader(1)
129 147
 test_asmi_reader(2)
  148
+test_asmi_writer(1)
  149
+test_asmi_writer(2)
79  migen/actorlib/dma_asmi.py
@@ -76,8 +76,87 @@ def __init__(self, port):
76 76
 			rob.tag_call.eq(port.tag_call)
77 77
 		]
78 78
 
  79
+class SequentialWriter(Module):
  80
+	def __init__(self, port):
  81
+		assert(len(port.slots) == 1)
  82
+		self.address_data = Sink([("a", port.hub.aw), ("d", port.hub.dw)])
  83
+		self.busy = Signal()
  84
+
  85
+		###
  86
+
  87
+		data_reg = Signal(port.hub.dw)
  88
+		self.comb += [
  89
+			port.adr.eq(self.address_data.payload.a),
  90
+			port.we.eq(1),
  91
+			port.stb.eq(self.address_data.stb),
  92
+			self.address_data.ack.eq(port.ack)
  93
+		]
  94
+		self.sync += [
  95
+			port.dat_w.eq(0),
  96
+			If(port.get_call_expression(),
  97
+				self.busy.eq(0),
  98
+				port.dat_w.eq(data_reg)
  99
+			),
  100
+			If(self.address_data.stb & self.address_data.ack,
  101
+				self.busy.eq(1),
  102
+				data_reg.eq(self.address_data.payload.d)
  103
+			)
  104
+		]
  105
+
  106
+class _WriteSlot(Module):
  107
+	def __init__(self, port, n):
  108
+		self.load_data = Signal(port.hub.dw)
  109
+		self.busy = Signal()
  110
+
  111
+		###
  112
+
  113
+		drive_data = Signal()
  114
+		data_reg = Signal(port.hub.dw)
  115
+		self.comb += If(drive_data, port.dat_w.eq(data_reg))
  116
+
  117
+		self.sync += [
  118
+			If(port.stb & port.ack & (port.tag_issue == (port.base + n)),
  119
+				self.busy.eq(1),
  120
+				data_reg.eq(self.load_data)
  121
+			),
  122
+			drive_data.eq(0),
  123
+			If(port.get_call_expression(n),
  124
+				self.busy.eq(0),
  125
+				drive_data.eq(1)
  126
+			)
  127
+		]
  128
+
  129
+class OOOWriter(Module):
  130
+	def __init__(self, port):
  131
+		assert(len(port.slots) > 1)
  132
+		self.address_data = Sink([("a", port.hub.aw), ("d", port.hub.dw)])
  133
+		self.busy = Signal()
  134
+
  135
+		###
  136
+
  137
+		self.comb += [
  138
+			port.adr.eq(self.address_data.payload.a),
  139
+			port.we.eq(1),
  140
+			port.stb.eq(self.address_data.stb),
  141
+			self.address_data.ack.eq(port.ack)
  142
+		]
  143
+
  144
+		busy = 0
  145
+		for i in range(len(port.slots)):
  146
+			write_slot = _WriteSlot(port, i)
  147
+			self.submodules += write_slot
  148
+			self.comb += write_slot.load_data.eq(self.address_data.payload.d)
  149
+			busy = busy | write_slot.busy
  150
+		self.comb += self.busy.eq(busy)
  151
+
79 152
 def Reader(port):
80 153
 	if len(port.slots) == 1:
81 154
 		return SequentialReader(port)
82 155
 	else:
83 156
 		return OOOReader(port)
  157
+
  158
+def Writer(port):
  159
+	if len(port.slots) == 1:
  160
+		return SequentialWriter(port)
  161
+	else:
  162
+		return OOOWriter(port)

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