bank: remove RE signal for field registers

migen/bank/csrgen.py

@@ -29,15 +29,13 @@ def get_fragment(self):
 					self.interface.we & \
 					(self.interface.adr[:nbits] == Constant(i, BV(nbits)))))
 			elif isinstance(reg, RegisterFields):
-				sync.append(reg.re.eq(0))
 				bwra = [Constant(i, BV(nbits))]
 				offset = 0
 				for field in reg.fields:
 					if field.access_bus == WRITE_ONLY or field.access_bus == READ_WRITE:
 						bwra.append(field.storage.eq(self.interface.dat_w[offset:offset+field.size]))
 					offset += field.size
 				if len(bwra) > 1:
-					bwra.append(reg.re.eq(1))
 					bwcases.append(bwra)
 				# commit atomic writes
 				for field in reg.fields:

migen/bank/description.py

@@ -28,13 +28,9 @@ def __init__(self, name, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, re
 				self.we = Signal()
 
 class RegisterFields:
-	def __init__(self, name, fields, re=None):
+	def __init__(self, name, fields):
 		self.name = name
 		self.fields = fields
-		if re is None:
-			self.re = Signal()
-		else:
-			self.re = re
 
 class RegisterField(RegisterFields):
 	def __init__(self, name, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0, atomic_write=False):
@@ -111,7 +107,7 @@ def expand_description(description, busword):
 				else:
 					f.append(field)
 			if f:
-				d.append(RegisterFields(reg.name, f, reg.re))
+				d.append(RegisterFields(reg.name, f))
 		else:
 			raise TypeError
 	return d