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csr/SRAM: support for writes with memory widths larger than bus words

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commit b75fb7f97c5e69d6756ac20c0f1000b5cbdc757a 1 parent 6fa3005
Sébastien Bourdeauducq authored March 09, 2013

Showing 1 changed file with 19 additions and 4 deletions. Show diff stats Hide diff stats

  1. 23  migen/bus/csr.py
23  migen/bus/csr.py
@@ -54,7 +54,7 @@ def _compute_page_bits(nwords):
54 54
 		return 0
55 55
 
56 56
 class SRAM:
57  
-	def __init__(self, mem_or_size, address, bus=None):
  57
+	def __init__(self, mem_or_size, address, read_only=None, bus=None):
58 58
 		if isinstance(mem_or_size, Memory):
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 			self.mem = mem_or_size
60 60
 		else:
@@ -71,6 +71,12 @@ def __init__(self, mem_or_size, address, bus=None):
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 			self._page = RegisterField(self.mem.name_override + "_page", page_bits)
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 		else:
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 			self._page = None
  74
+		if read_only is None:
  75
+			if hasattr(self.mem, "bus_read_only"):
  76
+				read_only = self.mem.bus_read_only
  77
+			else:
  78
+				read_only = False
  79
+		self.read_only = read_only
74 80
 		if bus is None:
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 			bus = Interface()
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 		self.bus = bus
@@ -82,7 +88,8 @@ def get_registers(self):
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 			return [self._page]
83 89
 	
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 	def get_fragment(self):
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-		port = self.mem.get_port(write_capable=not self.word_bits)
  91
+		port = self.mem.get_port(write_capable=not self.read_only,
  92
+			we_granularity=data_width if not self.read_only and self.word_bits else 0)
86 93
 		
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 		sel = Signal()
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 		sel_r = Signal()
@@ -99,14 +106,22 @@ def get_fragment(self):
99 106
 					chooser(word_expanded, word_index, self.bus.dat_r, n=self.csrw_per_memw, reverse=True)
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 				)
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 			]
  109
+			if not self.read_only:
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+				comb += [
  111
+					If(sel & self.bus.we, port.we.eq((1 << self.word_bits) >> self.bus.adr[:self.word_bits])),
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+					port.dat_w.eq(Replicate(self.bus.dat_w, self.csrw_per_memw))
  113
+				]
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 		else:
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 			comb += [
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-				port.we.eq(sel & self.bus.we),
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-				port.dat_w.eq(self.bus.dat_w),
106 116
 				If(sel_r,
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 					self.bus.dat_r.eq(port.dat_r)
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 				)
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 			]
  120
+			if not self.read_only:
  121
+				comb += [
  122
+					port.we.eq(sel & self.bus.we),
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+					port.dat_w.eq(self.bus.dat_w)
  124
+				]
110 125
 		
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 		if self._page is None:
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 			comb.append(port.adr.eq(self.bus.adr[self.word_bits:len(port.adr)]))

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