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Cat(..)[slice] on LHS needs a proxy #20
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A workaround to using Record.raw_bits() is to iterate over a record's subsignals using Record.iter_flat(). Using the above gist as an example, replace the line
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I suspect that the solution here is to reaffirm that migen does not guarantee syntactictally valid verilog. |
@jordens You may be right. FWIW, I have found another edge case where the same invalid Verilog idiom will be generated when dealing with tristates: https://gist.github.com/cr1901/3a666c635f956fa6a819 |
Triage: fixed in nMigen. |
When attempting to use Record.raw_bits() to create a bus to manipulate in further Migen expressions, Migen will generate the concatenation "in place" in the generated Verilog code for each use of the bus instead of assigning to a temporary bus.
E.g. Assuming a record with fields a, b, c, d of varying widths and used as inouts, Migen will generate:
for each use of the Signal created from Record.raw_bits(), as opposed to:
While the generated Verilog code in the former may be syntactically valid, some vendors may reject such assignments anyway- Xilinx's compiler (when use_new_parser=YES, as it should be for Migen) is known to choke on these assignments.
See the following gist for the code I was trying to synthesize when I ran into this issue: https://gist.github.com/cr1901/c994d2d307a35f1344ac
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