Reverted to old VGA, new one does not work

m-labs · Jan 10, 2010 · e5a7c92 · e5a7c92
1 parent b457ddf
commit e5a7c92
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Showing 5 changed files with 27 additions and 94 deletions.
diff --git a/boards/xilinx-ml401/rtl/setup.v b/boards/xilinx-ml401/rtl/setup.v
@@ -23,9 +23,9 @@
  */
 
 `define ENABLE_ACEUSB
-`define ENABLE_AC97
-`define ENABLE_PFPU
-`define ENABLE_TMU
+//`define ENABLE_AC97
+//`define ENABLE_PFPU
+//`define ENABLE_TMU
 `define ENABLE_PS2_KEYBOARD
 `define ENABLE_PS2_MOUSE
 

diff --git a/boards/xilinx-ml401/rtl/vga.v b/boards/xilinx-ml401/rtl/vga.v
@@ -1,7 +1,6 @@
 /*
  * Milkymist VJ SoC
  * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- * Copyright (C) 2009 Takeshi Matsuya
  *
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -36,7 +35,7 @@ module vga #(
 	output fml_stb,
 	input fml_ack,
 	input [63:0] fml_di,
-
+	
 	/* VGA pads */
 	output vga_psave_n,
 	output vga_hsync_n,
@@ -49,87 +48,13 @@ module vga #(
 	output vga_clkout
 );
 
-wire vga_clk1, vga_clk2;
+wire vga_clk;
 
 reg [1:0] fcounter;
-wire [1:0] vga_clk_sel;
 always @(posedge sys_clk) fcounter <= fcounter + 2'd1;
+assign vga_clk = fcounter[1];
 
-wire clk0;
-wire clk0_bufg;
-BUFG i_bufg_clk0 (
-	.I(clk0),
-	.O(clk0_bufg)
-);
-
-// Generate 50MHz
-wire clkdv;
-wire clkdv_bufg;
-BUFG i_bufg_clkdv (
-	.I(clkdv),
-	.O(clkdv_bufg)
-);
-
-// Generate 65MHz
-wire clkfx;
-wire clkfx_bufg;
-BUFG i_bufg_clkfx (
-	.I(clkfx),
-	.O(clkfx_bufg)
-);
-
-DCM #(
-	.CLK_FEEDBACK("1X"),
-	.CLKDV_DIVIDE(2.0),
-	.CLKFX_DIVIDE(20), // 100MHz*20/13=65MHz
-	.CLKFX_MULTIPLY(13),
-	.CLKIN_DIVIDE_BY_2("FALSE"),
-	.CLKIN_PERIOD(20.000),
-	.CLKOUT_PHASE_SHIFT("NONE"),
-	.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
-	.DFS_FREQUENCY_MODE("LOW"),
-	.DLL_FREQUENCY_MODE("LOW"),
-	.DUTY_CYCLE_CORRECTION("TRUE"),
-	.FACTORY_JF(16'hF0F0),
-	.PHASE_SHIFT(0),
-	.STARTUP_WAIT("FALSE")
-) i_dcm (
-	.CLKFB(clk0_bufg),
-	.CLKIN(sys_clk),
-	.DSSEN(1'b0),
-	.PSCLK(1'b0),
-	.PSEN(1'b0),
-	.PSINCDEC(1'b0),
-	.RST(in_reset),
-	.CLKDV(clkdv),
-	.CLKFX(clkfx),
-	.CLKFX180(),
-	.CLK0(clk0),
-	.CLK2X(clk2x),
-	.CLK2X180(),
-	.CLK90(),
-	.CLK180(),
-	.CLK270(),
-	.LOCKED(),
-	.PSDONE(),
-	.STATUS()
-);
-
-BUFGMUX BUFGMUX_vgaclk1 (
-	.O(vga_clk1),
-	.I0(fcounter[1]),
-	.I1(clkdv_bufg),
-	.S(vga_clk_sel[0])
-);
-
-BUFGMUX BUFGMUX_vgaclk2 (
-	.O(vga_clk2),
-	.I0(vga_clk1),
-	.I1(clkfx_bufg),
-	.S(vga_clk_sel[1])
-);
-
-assign vga_clkout = vga_clk2;
+assign vga_clkout = vga_clk;
 
 vgafb #(
 	.csr_addr(csr_addr),
@@ -148,16 +73,15 @@ vgafb #(
 	.fml_ack(fml_ack),
 	.fml_di(fml_di),
 
-	.vga_clk(vga_clk2),
+	.vga_clk(vga_clk),
 	.vga_psave_n(vga_psave_n),
 	.vga_hsync_n(vga_hsync_n),
 	.vga_vsync_n(vga_vsync_n),
 	.vga_sync_n(vga_sync_n),
 	.vga_blank_n(vga_blank_n),
 	.vga_r(vga_r),
 	.vga_g(vga_g),
-	.vga_b(vga_b),
-	.vga_clk_sel(vga_clk_sel)
+	.vga_b(vga_b)
 );
 
 endmodule
diff --git a/boards/xilinx-ml401/sources.mak b/boards/xilinx-ml401/sources.mak
@@ -27,7 +27,8 @@ SYSCTL_SRC=$(wildcard $(CORES_DIR)/sysctl/rtl/*.v)
 ACEUSB_SRC=$(wildcard $(CORES_DIR)/aceusb/rtl/*.v)
 HPDMC_SRC=$(wildcard $(CORES_DIR)/hpdmc_ddr32/rtl/*.v) $(wildcard $(CORES_DIR)/hpdmc_ddr32/rtl/virtex4/*.v)
 VGAFB_SRC=						\
-	$(CORES_DIR)/vgafb/rtl/vgafb_asfifo_xilinx.v	\
+	$(CORES_DIR)/vgafb/rtl/vgafb_graycounter.v	\
+	$(CORES_DIR)/vgafb/rtl/vgafb_asfifo.v		\
 	$(CORES_DIR)/vgafb/rtl/vgafb_pixelfeed.v	\
 	$(CORES_DIR)/vgafb/rtl/vgafb_ctlif.v		\
 	$(CORES_DIR)/vgafb/rtl/vgafb_fifo64to16.v	\

diff --git a/cores/vgafb/rtl/vgafb.v b/cores/vgafb/rtl/vgafb.v
@@ -191,7 +191,7 @@ wire [17:0] fifo_do;
 
 vgafb_asfifo #(
 	.DATA_WIDTH(18),
-	.ADDRESS_WIDTH(11)
+	.ADDRESS_WIDTH(6)
 ) fifo (
 	.Data_out(fifo_do),
 	.Empty_out(),
@@ -203,7 +203,7 @@ vgafb_asfifo #(
 	.WriteEn_in(generate_en),
 	.WClk(sys_clk),
 
-	.Clear_in(sys_rst)
+	.Clear_in(vga_rst)
 );
 
 /*

diff --git a/cores/vgafb/rtl/vgafb_asfifo_xilinx.v b/cores/vgafb/rtl/vgafb_asfifo_xilinx.v
@@ -15,6 +15,8 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+/* FIXME: this module does not work. Find out why. */
+
 module vgafb_asfifo #(
 	/* NB: those are fixed in this implementation */
 	parameter DATA_WIDTH = 18,
@@ -35,6 +37,9 @@ module vgafb_asfifo #(
 	input Clear_in
 );
 
+wire full;
+wire empty;
+
 FIFO16 #(
 	.DATA_WIDTH(9),
 	.FIRST_WORD_FALL_THROUGH("TRUE")
@@ -43,21 +48,24 @@ FIFO16 #(
 	.ALMOSTFULL(),
 	.DO(Data_out[7:0]),
 	.DOP(Data_out[8]),
-	.EMPTY(Empty_out),
-	.FULL(Full_out),
+	.EMPTY(empty),
+	.FULL(full),
 	.RDCOUNT(),
 	.RDERR(),
 	.WRCOUNT(),
 	.WRERR(),
 	.DI(Data_in[7:0]),
 	.DIP(Data_in[8]),
 	.RDCLK(RClk),
-	.RDEN(ReadEn_in),
+	.RDEN(ReadEn_in & ~empty & ~Clear_in),
 	.RST(Clear_in),
 	.WRCLK(WClk),
-	.WREN(WriteEn_in)
+	.WREN(WriteEn_in & ~full & ~Clear_in)
 );
 
+assign Empty_out = empty;
+assign Full_out = full;
+
 FIFO16 #(
 	.DATA_WIDTH(9),
 	.FIRST_WORD_FALL_THROUGH("TRUE")
@@ -75,10 +83,10 @@ FIFO16 #(
 	.DI(Data_in[16:9]),
 	.DIP(Data_in[17]),
 	.RDCLK(RClk),
-	.RDEN(ReadEn_in),
+	.RDEN(ReadEn_in & ~empty & ~Clear_in),
 	.RST(Clear_in),
 	.WRCLK(WClk),
-	.WREN(WriteEn_in)
+	.WREN(WriteEn_in & ~full & ~Clear_in)
 );
 
 endmodule