use Migen s6ddrphy, generate sdram init_sequence in cif.py

make.py

@@ -27,7 +27,7 @@ def build(platform_name, build_bitstream, build_header):
 TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
 """)
 
-	for d in ["mxcrg", "s6ddrphy", "minimac3"]:
+	for d in ["mxcrg", "minimac3"]:
 		platform.add_source_dir(os.path.join("verilog", d))
 	platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"), 
 		"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
@@ -47,12 +47,16 @@ def build(platform_name, build_bitstream, build_header):
 	if build_header:
 		csr_header = cif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map)
 		write_to_file("software/include/hw/csr.h", csr_header)
+
+		sdram_phy_header = cif.get_sdram_phy_header(soc.ddrphy)
+		write_to_file("software/include/hw/sdram_phy.h", sdram_phy_header)
+
 
 def main():
 	parser = argparse.ArgumentParser(description="milkymist-ng - a high performance SoC built on Migen technology.")
 	parser.add_argument("-p", "--platform", default="mixxeo", help="platform to build for")
 	parser.add_argument("-B", "--no-bitstream", default=False, action="store_true", help="do not build bitstream file")
-	parser.add_argument("-H", "--no-header", default=False, action="store_true", help="do not build C header file with CSR/IRQ defs")
+	parser.add_argument("-H", "--no-header", default=False, action="store_true", help="do not build C header file with CSR/IRQ/SDRAM_PHY defs")
 	parser.add_argument("-l", "--load", default=False, action="store_true", help="load bitstream to SRAM")
 	parser.add_argument("-f", "--flash", default=False, action="store_true", help="load bitstream to flash")
 	args = parser.parse_args()

milkymist/cif.py

@@ -1,6 +1,7 @@
 from operator import itemgetter
 import re
 
+from migen.fhdl.std import *
 from migen.bank.description import CSRStatus
 
 def get_macros(filename):
@@ -64,3 +65,137 @@ def get_csr_header(csr_base, bank_array, interrupt_map):
 			r += "#define "+name.upper()+"_INTERRUPT "+str(interrupt_nr)+"\n"
 	r += "\n#endif\n"
 	return r
+
+def get_sdram_phy_header(sdram_phy):
+
+		if sdram_phy.phy_settings.type not in ["SDR", "DDR", "LPDDR", "DDR2"]:
+			raise NotImplementedError("sdram phy header generator only supports SDR, DDR, LPDDR and DDR2")
+
+		r = "#ifndef __HW_SDRAM_PHY_H\n#define __SDRAM_PHY_H\n"
+		r += "#include <hw/common.h>\n#include <hw/csr.h>\n#include <hw/flags.h>\n\n"
+
+		r += "extern void cdelay(int i);\n"
+
+		#
+		# commands_px functions
+		# 
+		for n in range(sdram_phy.phy_settings.nphases):
+			r += """
+static void command_p{n}(int cmd)
+{{
+	dfii_pi{n}_command_write(cmd);
+	dfii_pi{n}_command_issue_write(1);
+}}""".format(n=str(n))
+		r += "\n\n"
+
+		#
+		# rd/wr access macros
+		#
+		r += """
+#define dfii_pird_address_write(X) dfii_pi{rdphase}_address_write(X)
+#define dfii_piwr_address_write(X) dfii_pi{wrphase}_address_write(X)
+
+#define dfii_pird_baddress_write(X) dfii_pi{rdphase}_baddress_write(X)
+#define dfii_piwr_baddress_write(X) dfii_pi{wrphase}_baddress_write(X)
+
+#define command_prd(X) command_p{rdphase}(X)
+#define command_pwr(X) command_p{wrphase}(X)
+""".format(rdphase=str(sdram_phy.phy_settings.rdphase), wrphase=str(sdram_phy.phy_settings.wrphase)) 
+		r +="\n"
+
+		#
+		# init sequence
+		# 
+		cmds = {
+			"PRECHARGE_ALL" : "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
+			"MODE_REGISTER" : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
+			"AUTO_REFRESH"  : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS",
+			"CKE"           : "DFII_CONTROL_CKE"
+		}
+
+		def gen_cmd(comment, a, ba, cmd, delay):	
+			r = "\t/* %s */\n" %comment
+			r += "\tdfii_pi0_address_write(0x%04X);\n" %a
+			r += "\tdfii_pi0_baddress_write(%d);\n" %ba
+			if "CKE" in cmd:
+				r += "\tdfii_control_write(%s);\n" %cmd
+			else:
+				r += "\tcommand_p0(%s);\n" %cmd
+			r += "\tcdelay(%d);\n" %delay
+			r += "\n"
+			return r
+
+
+		r += "static void init_sequence(void) {\n"
+
+		cl = sdram_phy.phy_settings.cl
+
+		if sdram_phy.phy_settings.type == "SDR":
+			bl = 1*sdram_phy.phy_settings.nphases
+			mr  = log2_int(bl) + (cl << 4)
+			reset_dll = 1 << 8
+
+			init_sequence = [
+				("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
+				("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
+				("Load Mode Register / Reset DLL, CL=%d, BL=%d" %(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
+				("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
+				("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
+				("Load Mode Register / CL=%d, BL=%d" %(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
+			]
+
+		elif sdram_phy.phy_settings.type == "DDR":
+			bl = 2*sdram_phy.phy_settings.nphases
+			mr  = log2_int(bl) + (cl << 4)
+			emr = 0
+			reset_dll = 1 << 8
+
+			init_sequence = [
+				("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
+				("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
+				("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
+				("Load Mode Register / Reset DLL, CL=%d, BL=%d" %(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
+				("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
+				("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
+				("Load Mode Register / CL=%d, BL=%d" %(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
+			]
+
+		elif sdram_phy.phy_settings.type == "LPDDR":
+			bl = 2*sdram_phy.phy_settings.nphases
+			mr  = log2_int(bl) + (cl << 4)
+			emr = 0
+			reset_dll = 1 << 8
+
+			init_sequence = [
+				("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
+				("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
+				("Load Extended Mode Register", emr, 2, cmds["MODE_REGISTER"], 0),
+				("Load Mode Register / Reset DLL, CL=%d, BL=%d" %(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
+				("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
+				("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
+				("Load Mode Register / CL=%d, BL=%d" %(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
+			]
+
+		elif sdram_phy.phy_settings.type == "DDR2":
+			bl = 2*sdram_phy.phy_settings.nphases
+			mr  = log2_int(bl) + (cl << 4)
+			emr = 0
+			reset_dll = 1 << 8
+
+			init_sequence = [
+				("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
+				("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
+				("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
+				("Load Mode Register / Reset DLL, CL=%d, BL=%d" %(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
+				("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
+				("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
+				("Load Mode Register / CL=%d, BL=%d" %(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
+			]
+
+		for comment, a, ba, cmd, delay in init_sequence:
+			r += gen_cmd(comment, a, ba, cmd, delay)
+
+		r += "}\n"
+		r += "#endif\n"
+
+		return r

milkymist/lasmicon/__init__.py

@@ -7,7 +7,7 @@
 from milkymist.lasmicon.bankmachine import *
 from milkymist.lasmicon.multiplexer import *
 
-PhySettings = namedtuple("PhySettings", "dfi_d nphases rdphase wrphase")
+PhySettings = namedtuple("PhySettings", "type dfi_d nphases rdphase wrphase cl")
 
 class GeomSettings(namedtuple("_GeomSettings", "bank_a row_a col_a")):
 	def __init__(self, *args, **kwargs):

milkymist/mxcrg/__init__.py

@@ -6,9 +6,9 @@
 class MXCRG(Module, AutoCSR):
 	def __init__(self, pads, outfreq1x):
 		self.clock_domains.cd_sys = ClockDomain()
-		self.clock_domains.cd_sys2x_270 = ClockDomain()
-		self.clock_domains.cd_sys4x_wr = ClockDomain()
-		self.clock_domains.cd_sys4x_rd = ClockDomain()
+		self.clock_domains.cd_sdram_half = ClockDomain()
+		self.clock_domains.cd_sdram_full_wr = ClockDomain()
+		self.clock_domains.cd_sdram_full_rd = ClockDomain()
 		self.clock_domains.cd_eth_rx = ClockDomain()
 		self.clock_domains.cd_eth_tx = ClockDomain()
 		self.clock_domains.cd_vga = ClockDomain(reset_less=True)
@@ -44,9 +44,9 @@ def __init__(self, pads, outfreq1x):
 
 			Instance.Output("sys_clk", self.cd_sys.clk),
 			Instance.Output("sys_rst", self.cd_sys.rst),
-			Instance.Output("clk2x_270", self.cd_sys2x_270.clk),
-			Instance.Output("clk4x_wr", self.cd_sys4x_wr.clk),
-			Instance.Output("clk4x_rd", self.cd_sys4x_rd.clk),
+			Instance.Output("clk2x_270", self.cd_sdram_half.clk),
+			Instance.Output("clk4x_wr", self.cd_sdram_full_wr.clk),
+			Instance.Output("clk4x_rd", self.cd_sdram_full_rd.clk),
 			Instance.Output("eth_rx_clk", self.cd_eth_rx.clk),
 			Instance.Output("eth_tx_clk", self.cd_eth_tx.clk),
 			Instance.Output("vga_clk", self.cd_vga.clk),