liteeth: remove dw parameterization

[sbourdeauducq]

The data path width parameter is dragged around the core but the difficult issues (e.g. unaligned SFD, unaligned CRC) are not addressed. Having a configurable data path width is not straightforward and has little practical value, all current PHYs are 1-byte wide. The parameter should be removed to reduce complexity/clutter a bit and stop giving the false impression that the core supports dw != 8.

[whitequark]

SaymaAMC, Kasli and KC705 MiniSoCs currently use dw=32.

[sbourdeauducq]

That's the dw for the PHY. That one is 8 everywhere AFAIK. Where do you see 32?