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hdl.mem: remove WritePort(priority=) argument.
The write port priority in Yosys is derived directly from the order in which the ports are declared in the Verilog frontend. It is being removed for several reasons: 1. It is not clear if it works correctly for all cases (FFRAM, LUTRAM, BRAM). 2. Although it is roundtripped via Verilog with correct simulation semantics, the resulting code has a high chance of being interpreted incorrectly by Xilinx tools. 3. It cannot be roundtripped via FIRRTL, which is an alternative backend that is an interesting future option. (FIRRTL leaves write collision completely undefined.) 3. It is a niche feature that, if it is needed, can be completely replaced using an explicit comparator, priority encoder, and write enable gating circuit. (This is what Xilinx recommends for handling this case.) In the future we should extend nMigen's formal verification to assert that a write collision does not happen.
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