Fixed #1 Improved method to separate elements

m47812 · Apr 3, 2022 · a0b7fd2 · a0b7fd2
1 parent 46683d7
commit a0b7fd2
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Showing 3 changed files with 62 additions and 15 deletions.
diff --git a/HDL_Converter_App/HDL_Converter_Classes/HDL_Structures/VerilogConstructs.cs b/HDL_Converter_App/HDL_Converter_Classes/HDL_Structures/VerilogConstructs.cs
@@ -59,15 +59,7 @@ protected override void initializeWires(string hdlCode)
     /// A Wire in the Verilog domain serving as an IO to a module
     /// </summary>
     public class VeriWire : Wire
-    {
-        /// <summary>
-        /// Separates a string of HDL Code into Wire Components
-        /// </summary>
-        /// <param name="hdlCode">A HDL code segment (the part that is inbetween the parenthesi 
-        /// containing the module IO declaration
-        /// </param>
-        /// <returns>A List of string arrays each array containing the module code at index 0
-        /// and (if available) a comment at index 1</returns>
+    {        
         public static List<string[]> separateElements(string hdlCode)
         {
             string[] splited = hdlCode.Split(',');
@@ -144,6 +136,7 @@ public override string generateWireDeclarationLine()
     /// </summary>
     public class VeriParameter : Parameter
     {
+
         public override string generateInstantiationLine()
         {
             string commandLine;
@@ -163,4 +156,48 @@ public override string generateWireDeclarationLine()
             return "localparam " + this.name +" = "+this.value+ ";";
         }
     }
+
+    public static class VeriDataProcessing
+    {
+        /// <summary>
+        /// Separates a string of HDL Code into Wire Components
+        /// </summary>
+        /// <param name="hdlCode">A HDL code segment (the part that is inbetween the parenthesi 
+        /// containing the module IO declaration
+        /// </param>
+        /// <returns>A List of string arrays each array containing the module code at index 0
+        /// and (if available) a comment at index 1</returns>
+        public static List<string[]> separateElements(string hdlCode)
+        {
+            List<string[]> retList = new List<string[]>();
+            string[] hdlSplited = hdlCode.Replace("//", "//{Comment}").Split(new string[] { System.Environment.NewLine, "//" }, StringSplitOptions.None);
+            foreach (string element in hdlSplited)
+            {
+                if (element.Trim() == "") continue;
+                if (!element.Contains("{Comment}"))
+                {
+                    string[] splitedAtComma = element.Trim().Split(new char[] { ',' }, StringSplitOptions.RemoveEmptyEntries);
+                    foreach(string commaSpearated in splitedAtComma)
+                    {
+                        string[] nextEntry = new string[2];
+                        nextEntry[0] = commaSpearated.Replace(',', ' ').Trim();
+                        nextEntry[1] = "";
+                        retList.Add(nextEntry);
+                    }                    
+                }
+                else
+                {
+                    if (retList.Last()[1] != "")
+                    {
+                        string[] nextEntry = new string[2];
+                        nextEntry[0] = "";
+                        nextEntry[1] = "";
+                        retList.Add(nextEntry);
+                    }
+                    retList.Last()[1] = element.Replace("{Comment}", " ").Trim();
+                }
+            }
+            return retList;
+        }
+    }
 }
diff --git a/HDL_Converter_App/HDL_Converter_Test/Test_Data/Verilog_Wire_Separate_Elements.txt b/HDL_Converter_App/HDL_Converter_Test/Test_Data/Verilog_Wire_Separate_Elements.txt
@@ -7,8 +7,18 @@ input wire we, //Comment 1
 input wire[4:0] addr, //Comment 2
 input wire[5:0] someSig,
 output wire[255:0] otherSig //Comment 3
-$input wire we|//Comment 1|input wire[4:0] addr|//Comment 2|input wire[5:0] someSig||output wire[255:0] otherSig|//Comment 3$
-input wire we, //I // wirte / more/ comm,ts
+$input wire we|Comment 1|input wire[4:0] addr|Comment 2|input wire[5:0] someSig||output wire[255:0] otherSig|Comment 3$
+input wire we, //I / wirte / more/ comm,ts
 input wire[4:0] addr, //Comment 2
-input wire[5:0] someSig //I / like / to //Implant, tese
-$input wire we|//I // wirte / more/ comm ts|input wire[4:0] addr|//Comment 2|input wire[5:0] someSig|//I / like / to //Implant  tese
+input wire[5:0] someSig //I / like / to /Implant, tese
+$input wire we|I / wirte / more/ comm,ts|input wire[4:0] addr|Comment 2|input wire[5:0] someSig|I / like / to /Implant, tese$
+input wire we,  input wire[4:0] addr, input wire[5:0] someSig, output wire[255:0] otherSig
+$input wire we||input wire[4:0] addr||input wire[5:0] someSig||output wire[255:0] otherSig|$
+parameter param1 = 12,
+parameter param2 = 2,
+parameter param3 = 'h0A
+$parameter param1 = 12||parameter param2 = 2||parameter param3 = 'h0A|$
+parameter param1 = 12, //Comment 1
+parameter param2 = 2,  
+parameter param3 = 'h0A  //Comment 2
+$parameter param1 = 12|Comment 1|parameter param2 = 2||parameter param3 = 'h0A|Comment 2
diff --git a/HDL_Converter_App/HDL_Converter_Test/VerilogTests.cs b/HDL_Converter_App/HDL_Converter_Test/VerilogTests.cs
@@ -66,13 +66,13 @@ public void test_parameter_instantiation(string name, string resultWith, string
         }
 
         [TestMethod]
-        public void test_veriwire_separate_elements()
+        public void test_separate_elements()
         {
             string path = "@../../../../../Test_data/Verilog_Wire_Separate_Elements.txt";
             string[] fileContent = GeneralTests.load_testdata_from_file(path);
             for(int i = 0; i < fileContent.Length; i += 2)
             {
-                List<string[]> computed = VeriWire.separateElements(fileContent[i]);
+                List<string[]> computed = VeriDataProcessing.separateElements(fileContent[i]);
                 string[] expected = fileContent[i + 1].Split('|');
                 for(int j = 0; j < expected.Length; j++)
                 {