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A simple tool that can be used to convert the header syntax of a verilog module or VHDL entity to an instantiation syntax and create testbench structures (top level and verify). The project is aimed at removing the need for tedious refactoring of module headers when instantiating modules or verifying individual modules with testbenches.

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m47812/HDL_Converter

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HDL Converter

Title

License C#

A simple tool that can be used to convert the header syntax of a verilog module or VHDL Entity to an instantiation syntax and create testbench structures (top level and verify). The project is aimed at removing the need for tedious refactoring of module headers when instantiating modules or verifying individual modules with testbenches.

Feature Overview

Language Support

Verilog VHDL

Features Included

  • Conversion of Verilog or VHDL header/entity to instantiation of the module
  • Conversion of Verilog or VHDL header/entity to declare all wires in the module
  • Automatic generation of testbench structure (testbench toplevel, verify module)
  • Comment creation for instantiaton making port direction easily visible
  • Parsing of Verilog/VHDL header syntax to objects and attributes (easy expandability to othre hdl code generations functions)
  • Flexibility to support other HDL languages

Features Planed

  • Cross HDL Generation/Translation for existing functions
  • Updating of existing instantiations with new wires

How to Use

Release

You can finde the latest release versions executables here.

Installation

Unpack the .zip file of the version you would like to use (Console or GUI) to the desired location on your disk. Keep all other files contained in the zip file in the same folder. To use the app simply run the .exe file contained in the downloaded zip file.

Note for Console App: Note that, to run the Console app, you need the .Net Core Runtime Environment (Version 3.1) installed.

For more information on how to use the Tool please refer to the user guides.

Usage Example

Input:

module test
#(
parameter myParam1 = 12,
parameter myParam2 = 2
)
(
input wire clock,
input wire reset, //Comment
output wire [7:0] busOut,
inout wire someSignal //Comment
);

Generate Instance Output:

test inst_test
#(
	.myParam1(myParam1),
	.myParam2(myParam2)
)(
	.clock(clock),
	.reset(reset),
	.busOut(busOut),
	.someSignal(someSignal)
);

Generate Wire Declaration Output:

wire clock;
wire reset;
wire [7:0] busOut;
wire someSignal;

Testbench Creation:

Generates verify module with inverted IOs and connects them in a top level module. See Feature Guide for more information.

User Interface

GUI Based

GUI Example

Console Based

Console Example

Software Architecture

Class Diagramm

Contributors

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A simple tool that can be used to convert the header syntax of a verilog module or VHDL entity to an instantiation syntax and create testbench structures (top level and verify). The project is aimed at removing the need for tedious refactoring of module headers when instantiating modules or verifying individual modules with testbenches.

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