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Fixed Bug #744
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9518 35acf78f-673a-0410-8e92-d51de3d6d3f4
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roccomarco committed May 24, 2016
1 parent f738632 commit 2f4242a
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Showing 2 changed files with 14 additions and 7 deletions.
20 changes: 13 additions & 7 deletions os/hal/ports/STM32/STM32F4xx/hal_lld.h
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#define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */
#define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */

#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */

#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */
#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */
#define STM32_MCO1PRE_DIV2 (4 << 24) /**< MCO1 divided by 2. */
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#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */
/** @} */

/**
* @name RCC_PLLSAICFGR register bits definitions
* @{
*/
#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */

#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
/** @} */

/**
* @name RCC_BDCR register bits definitions
* @{
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1 change: 1 addition & 0 deletions readme.txt
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Expand Up @@ -113,6 +113,7 @@
- RT: Merged RT4.
- NIL: Merged NIL2.
- NIL: Added STM32F7 demo.
- HAL: Fixed wrong mask placement in STM32F4xx hal_lld.h (bug #744).
- HAL: Fixed wrong indent in STM32F4xx hal_lld.h (bug #743).
- HAL: Removed unused macros in STM32F7xx and STM32F4xx hal_lld.h (bug #742).
- HAL: Fixed Doxygen related macros in STM32F7xx, STM32L0xx and STM32L4xx
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