Static Timing Analysis - I

Static Timing Analysis

Section 1 - Introduction and Agenda

Checks

It is very important to identify a valid timing path.

A timing path should have a start point and an end point. Start point is either Flop clk pin or input ports End point is Flop d pin/ output ports

Refer to below image to get an idea of various timing paths in a circuit.

The abovee timing diagram shows 4 different timing paths

Arrival Time

Time required for a signal to reach at the end point from the start point.

When there are more than one possible start points for a particular end point, calculating the arrival point becomes tricky.

Required Time

Required time defines the needs of the system or the specifications of the system. Required time is the expected time for the signal to arrive.

For example,

These values are specified by the constraints and are the specifications to be met.

Slack

At a broad level, slack is the difference between the arrival time and the expected time.

In the above example, if we consider that the Signal should arrive after 0.5 ns and before 3ns, it implies that the arrival time should lie between 0.5 and 3 ns. Hence 0.5 ns can be considered as the minimum expected time and 3 ns can be considered as the maximum expected time. Also,let us suppose that the arrival time is 3.5ns. In this case, it satisfies one of the conditions and does not satisfy the other.

It meets the min constraint and does not meet the max constraint.

Min difference or min slack = Arrival time - Required time = 3.5 - 0.5 ns = 3ns

Refer below image

Max difference or max slack = Required time - arrival time = 3 - 3.5 = -0.5 ns --> This means that the signal is delayed by 0.5 ns and it needs to be taken care of.

Refer below image

Considering another example where min difference or minimum slack is not met. Refer below images.

Max slack is also referred to as setup slack or setup timing or setup analysis Min slack is referred to as hold slack or hold timing or hold analysis

So finally if the signal does not arrive within the given specifications, then it means there are some violations.

Types of Setup/ Hold analysis

1. reg2reg

Any path crossing from a register to register. In the below example, the path is from a launch flop to a capture flop

2. in2reg

Timing path between input port (not the clock ports) to D pin of the launch flop

3. reg2out

Timing path from capture flop output to output port

4. in2out

Timing path from input port to output port

There are many more categories for analysis

To understand the other categories, we finetune the circuit to include clock gating. the capture flop is not given the clock directly but through another circuit. The clock gating technique is widely used to to reduce the amount of chip power.

5. clock gating

As there is a new clock, there is a new timing path

Whenever the gating_signal is high, clock is given to the capture flop and when the gating_signal is 0, clock is not supplied to the capture flop.

This now involves a new category of analysis, known as clock gating analysis for the path between the new clock and the AND gate output

6. recovery/ removal

Considering asynchronous pins of the flop, for example, reset.

Recovery/ removal timing analysis involves the timing path is between the new clock and the reset pin. The reset signal should arrive after a particular time after the clock signal.

7. data-to-data

To save some amount of power in the reset path, the circuit is modified as below. A control signal is introduced to control the gating signal. Based on the A and control signal, the capture flop might be set or reset and hence some leakage power can be saved accordingly.

The specification is that the A and control signal should be in sync. The A and the control pin should be treated as end points. Then we get different timing paths corresponding to that, as shown below. These timing paths need a data check analysis. A timing path between 2 data signals is considered as data-to-data analysis.

The requirement could be that the A signal should arrive later than control signal and this can be ensured with this kind of timing analysis. Few constraints could be applied to meet this requirement.

8. latch (time borrow/ time given)

Launch flop becomes transparent at the edge of the clock signal. Latch becomes transparent at the level of the clock pulse.

If the timing path constraint from the flop to latch is not met, the flop can borrow some time from the area of level of the clock signal.

If the timing path constraint from the latch to the flop is not being met, some time can be given from the level of clock signal area to the start point i.e. the flop.

We also have the slew/ transition analysis, which have to met i.e., should be in between a particular min or max value.

Slew/ Transiiton Analysis

They are of 2 types:

• Data (max/ min)
• Clock

It is because the data doesn't change as frequently as the clock does. The clock has to change at equal intervals. Hence the clock transition requirements are stringent as compared to that of the data.

Data slew is calculated as slew along different points on data paths and are checked across min/max values.

The clock signal sent through the clock port, traverses through the entrire clock network. Hence it is bound to degrade. Therefore, the clock transition requirements are stringent. Slew is calculated across some points on the clock network and it values are verified across min/max values.

Load Analysis

It specifies what is the load at each and every node and also if the node is able to charge or dischrge that amount of load.

Load analysis is of 2 types

• Fanout (max/min) If the fanout is 3, the amount of load on the node will increase if it is able to carry that amount of load. There is max and min value for every node which depends on the capacitance it can drive.

• Capcitance (max/min)

  On the same end points, we can check the capcitances (if thery are within the required max and min values)

  

Clock analysis

It is broadly classified into

• Skew Difference between different clock networks is the skew. Refer the below diagram

• Pulse width

The clock pulse given at the clock port reaches the flops but with degradation due to parasitic capacitances. Pulse width analysis is required to understand how much can the clock pulse degarde for the circuit to still be working as exepcted. (i.e., if the clock pulse width reduces too much, then it might be not be even enough to load the data)

Section 2 - Introduction to timing graph

Types of setup/ hold analysis

1. reg2reg

Consider specifications as

Clock frequency (F) = 1GHz Clock Period (T) = 1/F = 1ns

and also consider below circuit for further analysis

Timing Analysis (with real clocks)

Setup Analysis - Single clock

Let's begin with the combinational logic

Converting the combinational circuit into a Directed Acyclic graph (DAG). This is known as timing graph in STA.

Timing graph is a representation of the complete circuit in nodes. using timing grpaphs, delays and arrival times can be calculated easily.

Note that the cell delay, wire delay and signal arrival time values are in units. (In real scenario, units are in pico seconds)

####Actual Arrival Time (AAT)

Calculating arrival times for all nodes

Few cell have more than one node as input, the arrival time for them is calculated as below

The selection of A1 or A2 depends on the type of analysis one is trying to do

Here since we are considering a reg2reg path, and the condition that arrival time should be less than max delay , we need to consider all worst case delays. Hence selecting A2 for the above example

After calculating all the arrival times in a similar fashion, below is the circuit digram.

Slack is computed is based on above timing graph.

####Required Arrival Time (RAT)

The term 'expect at latest transition' implies that they are the constraints or the specifications.

Difference between AAT and RAT

Where can this be helpful? To identify which node is giving the most negative slack if we see a negative slack at the output.

Let's assume or the system specification requires that the RAT isi 7.55 ns. Calculating the RATs for all the all nodes as below.

Which RAT to consider? Take the best case. Reason: If we consider the worst case to compute the slack i.e, required arrival time - actual arrival time , then there is a loss or optimism of few units. (Will be explained in detail in next sections)

The slack is defined as

Negative slack is shown as timing constraints violated

One way to remove negative slack to use a cell with same functionality with a different cell delay so as to accomodate the timing constraints. This is what is done in ECO (Engineering Change order)

The nodes i2(0), a(2), c(3) and d(2) can be toned to get a positive slack.

Consider d node for further analysis

GBA - worst case analysis PBA - considers actual paths that will be traced on silicon

In GBA, Slack is -0.35

In PBA, slack is +0.55

But this comes with a certain cost, ie.e., time to do the calculations. There is a run time impact (Will be explained in later sections)

For accurate and detailed timing analysis, DAG should be with pin node conventions. (i.e, each pin , inputs and outputs will have its own AAT, RAT and Slack)

For pin node conventions, all pin information needs to be extracted.

Section 3 - Clk-to-q delay, library setup, hold time

Check the transistor level circuitry for launch flop and capture flop.

But why?