Name		Name	Last commit message	Last commit date
Latest commit History 22 Commits
images		images
ALU.sv		ALU.sv
ALUCon_testbench.sv		ALUCon_testbench.sv
ALUControlUnit.sv		ALUControlUnit.sv
ALU_testbench.sv		ALU_testbench.sv
README.md		README.md
RISCV.sv		RISCV.sv
adder.sv		adder.sv
controlUnit.sv		controlUnit.sv
controlUnit_tb.sv		controlUnit_tb.sv
dataMem.sv		dataMem.sv
datapath.sv		datapath.sv
extend.sv		extend.sv
flopReg.sv		flopReg.sv
instructionMem.sv		instructionMem.sv
mainCon_tb.sv		mainCon_tb.sv
mainControlUnit.sv		mainControlUnit.sv
mux2.sv		mux2.sv
registers.sv		registers.sv
registers_tb.sv		registers_tb.sv

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Single Cycle RISCV processor

Computer Architecture final project

Instructions:

add
sub
beq (branch equal)
and
or
sd (store doubleword)
ld (load doubleword)

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Computer Architecture final project

systemverilog risc risc-v

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