Added Canton Electronics LX9 board

templates/null/boards/canton-lx9/board.cfg

@@ -0,0 +1,4 @@
+vendor: xilinx
+fpga: xc6slx9-tqg144-2
+map_flags:
+par_flags:

templates/null/boards/canton-lx9/board.ucf

@@ -0,0 +1,29 @@
+#
+# Copyright (C) 2009-2012 Chris McClelland
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU Lesser General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+#===============================================================================
+# System clock and a pair of LEDs
+#===============================================================================
+NET "sysClk_in"       LOC="P85"  | IOSTANDARD=LVTTL;   # SYS_CLK
+NET "led_out<0>"      LOC="P1"   | IOSTANDARD=LVTTL;
+NET "led_out<1>"      LOC="P2"   | IOSTANDARD=LVTTL;
+
+#===============================================================================
+# Timing constraint of FX2 48MHz clock "sysClk_in"
+#===============================================================================
+NET "sysClk_in" TNM_NET = "sysClk_in";
+TIMESPEC "TS_clk" = PERIOD "sysClk_in" 40 ns HIGH 50 %;

templates/null/boards/canton-lx9/board.ut

@@ -0,0 +1,30 @@
+-w
+-g DebugBitstream:No
+-g Binary:Yes
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:10
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4

templates/null/boards/canton-lx9/board.xst

@@ -0,0 +1,52 @@
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn top_level.prj
+-ofn top_level
+-ofmt NGC
+-p xc6slx9-2-tqg144
+-top top_level
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5

templates/null/boards/canton-lx9/fpga.batch

@@ -0,0 +1,5 @@
+setMode -bs
+setCable -port xsvf -file fpga.xsvf
+addDevice -p 1 -file top_level.bit
+program -p 1
+quit

vhdl/README

@@ -3,6 +3,7 @@ Examples of building the VHDL:
 ../../../../bin/hdlmake.py -t ../templates/null -b nexys2-1200 -p fpga
 ../../../../bin/hdlmake.py -t ../templates/null -b aes220
 ../../../../bin/hdlmake.py -t ../templates/null -b lx9 -p fpga
+../../../../bin/hdlmake.py -t ../templates/null -b canton-lx9 -p fpga
 ../../../../bin/hdlmake.py -t ../templates/null -b te630-45
 ../../../../bin/hdlmake.py -t ../templates/null -b te630-75
 ../../../../bin/hdlmake.py -t ../templates/null -b ep2c5 -p fpga