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namco/namcos12.cpp: Emulated games with CDXA board. (#11558)
* machine/t10mmc.cpp: Added support for T10SBC_CMD_SEEK_10 command. * cpu/sh: Added SH7014 SoC. * machine/icd2061a.cpp: Emulated IC Designs 2061A programmable clock generator. * sound/lc78836m.cpp: Emulated Sanyo LC78836M audio DAC. * namco/namcos12_cdxa.cpp: Emulated Namco System 12 CDXA board. Systems promoted to working ----------------------------- Truck Kyosokyoku (Japan, TKK2/VER.A) [Windy Fairy] New working systems ----------------------------- Um Jammer Lammy NOW! (Japan, UL1/VER.A) [Phil Bennett, Eric Yockey, Windy Fairy]
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// license:BSD-3-Clause | ||
// copyright-holders:windyfairy | ||
/*************************************************************************** | ||
SH-2 SH7014 | ||
***************************************************************************/ | ||
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#include "emu.h" | ||
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#include "sh7014.h" | ||
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DEFINE_DEVICE_TYPE(SH2_SH7014, sh2_sh7014_device, "sh2_sh7014", "Hitachi SH-2 (SH7014)") | ||
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sh2_sh7014_device::sh2_sh7014_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) | ||
: sh2_device(mconfig, SH2_SH7014, tag, owner, clock, CPU_TYPE_SH2, address_map_constructor(FUNC(sh2_sh7014_device::sh7014_map), this), 32, 0xffffffff) | ||
, m_sci(*this, "sci%u", 0u) | ||
, m_bsc(*this, "bsc") | ||
, m_dmac(*this, "dmac") | ||
, m_intc(*this, "intc") | ||
, m_mtu(*this, "mtu") | ||
, m_port(*this, "io_port") | ||
, m_sci_tx_cb(*this) | ||
{ | ||
} | ||
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void sh2_sh7014_device::device_start() | ||
{ | ||
sh2_device::device_start(); | ||
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save_item(NAME(m_ccr)); | ||
} | ||
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void sh2_sh7014_device::device_reset() | ||
{ | ||
sh2_device::device_reset(); | ||
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// CAC | ||
m_ccr = 0; | ||
} | ||
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void sh2_sh7014_device::device_add_mconfig(machine_config &config) | ||
{ | ||
SH7014_SCI(config, m_sci[0], DERIVED_CLOCK(1, 1), m_intc, | ||
0, // id | ||
sh7014_intc_device::INT_VECTOR_SCI_ERI0, | ||
sh7014_intc_device::INT_VECTOR_SCI_RXI0, | ||
sh7014_intc_device::INT_VECTOR_SCI_TXI0, | ||
sh7014_intc_device::INT_VECTOR_SCI_TEI0 | ||
); | ||
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SH7014_SCI(config, m_sci[1], DERIVED_CLOCK(1, 1), m_intc, | ||
1, // id | ||
sh7014_intc_device::INT_VECTOR_SCI_ERI1, | ||
sh7014_intc_device::INT_VECTOR_SCI_RXI1, | ||
sh7014_intc_device::INT_VECTOR_SCI_TXI1, | ||
sh7014_intc_device::INT_VECTOR_SCI_TEI1 | ||
); | ||
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SH7014_BSC(config, m_bsc); | ||
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SH7014_DMAC(config, m_dmac, DERIVED_CLOCK(1, 1), *this, m_intc); | ||
m_dmac->set_notify_dma_source_callback(FUNC(sh2_sh7014_device::notify_dma_source)); | ||
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SH7014_INTC(config, m_intc); | ||
m_intc->set_irq_callback(FUNC(sh2_sh7014_device::set_irq)); | ||
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SH7014_MTU(config, m_mtu, DERIVED_CLOCK(1, 1), m_intc); | ||
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SH7014_PORT(config, m_port); | ||
} | ||
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void sh2_sh7014_device::sh7014_map(address_map &map) | ||
{ | ||
// SCI - Serial Communication Interface | ||
map(0xffff81a0, 0xffff81af).m(m_sci[0], FUNC(sh7014_sci_device::map)); | ||
map(0xffff81b0, 0xffff81bf).m(m_sci[1], FUNC(sh7014_sci_device::map)); | ||
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// MTU - Multifunction Timer Pulse Unit | ||
map(0xffff8240, 0xffff82af).m(m_mtu, FUNC(sh7014_mtu_device::map)); | ||
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// INTC - Interrupt Controller | ||
map(0xffff8348, 0xffff835b).m(m_intc, FUNC(sh7014_intc_device::map)); | ||
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// I/O - I/O Ports (DR registers) | ||
// PFC - Pin Function Controller (IOR, CR registers) | ||
// TODO: SH7016/SH7017 support additionally C and D ports in addition to the A, B, E, F that the SH7014 supports | ||
map(0xffff8382, 0xffff8383).rw(m_port, FUNC(sh7014_port_device::padrl_r), FUNC(sh7014_port_device::padrl_w)); | ||
map(0xffff8386, 0xffff8387).rw(m_port, FUNC(sh7014_port_device::paiorl_r), FUNC(sh7014_port_device::paiorl_w)); | ||
map(0xffff838c, 0xffff838d).rw(m_port, FUNC(sh7014_port_device::pacrl1_r), FUNC(sh7014_port_device::pacrl1_w)); | ||
map(0xffff838e, 0xffff838f).rw(m_port, FUNC(sh7014_port_device::pacrl2_r), FUNC(sh7014_port_device::pacrl2_w)); | ||
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map(0xffff8390, 0xffff8391).rw(m_port, FUNC(sh7014_port_device::pbdr_r), FUNC(sh7014_port_device::pbdr_w)); | ||
map(0xffff8394, 0xffff8395).rw(m_port, FUNC(sh7014_port_device::pbior_r), FUNC(sh7014_port_device::pbior_w)); | ||
map(0xffff8398, 0xffff8399).rw(m_port, FUNC(sh7014_port_device::pbcr1_r), FUNC(sh7014_port_device::pbcr1_w)); | ||
map(0xffff839a, 0xffff839b).rw(m_port, FUNC(sh7014_port_device::pbcr2_r), FUNC(sh7014_port_device::pbcr2_w)); | ||
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map(0xffff83b0, 0xffff83b1).rw(m_port, FUNC(sh7014_port_device::pedr_r), FUNC(sh7014_port_device::pedr_w)); | ||
map(0xffff83b4, 0xffff83b5).rw(m_port, FUNC(sh7014_port_device::peior_r), FUNC(sh7014_port_device::peior_w)); | ||
map(0xffff83b8, 0xffff83b9).rw(m_port, FUNC(sh7014_port_device::pecr1_r), FUNC(sh7014_port_device::pecr1_w)); | ||
map(0xffff83ba, 0xffff83bb).rw(m_port, FUNC(sh7014_port_device::pecr2_r), FUNC(sh7014_port_device::pecr2_w)); | ||
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map(0xffff83b3, 0xffff83b3).r(m_port, FUNC(sh7014_port_device::pfdr_r)); | ||
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// TODO: CMT - Compare Match Timer | ||
// 0xffff83d0 - 0xffff83df | ||
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// TODO: A/D - A/D Converter (High Speed, for SH7014) | ||
// 0xffff83e0 - 0xffff83ff | ||
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// TODO: A/D - A/D Converter (Mid Speed, for SH7016/SH7017) | ||
// 0xffff8420 - 0xffff8429 | ||
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// TODO: WDT - Watchdog Timer | ||
// 0xffff8610 - 0xffff8613 | ||
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// TODO: Power-down state | ||
// 0xffff8614 | ||
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// BSC - Bus State Controller | ||
map(0xffff8620, 0xffff8633).m(m_bsc, FUNC(sh7014_bsc_device::map)); | ||
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// DMAC - Direct Memory Access Controller | ||
map(0xffff86b0, 0xffff86df).m(m_dmac, FUNC(sh7014_dmac_device::map)); | ||
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// CAC - Cache Memory | ||
map(0xffff8740, 0xffff8741).rw(FUNC(sh2_sh7014_device::ccr_r), FUNC(sh2_sh7014_device::ccr_w)); | ||
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// Cache space | ||
map(0xfffff000, 0xffffffff).ram(); | ||
} | ||
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void sh2_sh7014_device::sh2_exception_internal(const char *message, int irqline, int vector) | ||
{ | ||
// IRQ was taken so clear it in the interrupt controller and pass it down | ||
m_intc->set_interrupt(vector, CLEAR_LINE); | ||
sh2_device::sh2_exception_internal(message, irqline, vector); | ||
} | ||
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void sh2_sh7014_device::execute_set_input(int irqline, int state) | ||
{ | ||
/* | ||
Flow for SH7014 IRQs: | ||
sh2_sh7014_device::execute_set_input (for externally triggered IRQs) | ||
-> sh7014_intc_device::set_input | ||
-> sh2_sh7014_device::set_irq | ||
-> sh2_device::execute_set_input (if not internal peripheral IRQ) OR DMA interception OR set sh2_device's internal IRQ flags | ||
*/ | ||
m_intc->set_input(irqline, state); | ||
} | ||
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void sh2_sh7014_device::set_irq(int vector, int level, bool is_internal) | ||
{ | ||
if (!is_internal) { | ||
sh2_device::execute_set_input(vector, ASSERT_LINE); | ||
return; | ||
} | ||
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// SH7014's DMA controller can be configured to trigger based on various | ||
// on-board peripheral IRQs, so on-board peripheral IRQs must go through here | ||
if (m_dmac->is_dma_activated(vector)) { | ||
m_intc->set_interrupt(vector, CLEAR_LINE); | ||
return; | ||
} | ||
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m_sh2_state->internal_irq_level = level; | ||
m_internal_irq_vector = vector; | ||
m_test_irq = 1; | ||
} | ||
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void sh2_sh7014_device::notify_dma_source(uint32_t source) | ||
{ | ||
if (source == sh7014_dmac_channel_device::RS_SCI_TXI0) | ||
m_sci[0]->set_dma_source_tx(true); | ||
else if (source == sh7014_dmac_channel_device::RS_SCI_TXI1) | ||
m_sci[1]->set_dma_source_tx(true); | ||
else if (source == sh7014_dmac_channel_device::RS_SCI_RXI0) | ||
m_sci[0]->set_dma_source_rx(true); | ||
else if (source == sh7014_dmac_channel_device::RS_SCI_RXI1) | ||
m_sci[1]->set_dma_source_rx(true); | ||
} | ||
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/////// | ||
// CAC | ||
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uint16_t sh2_sh7014_device::ccr_r() | ||
{ | ||
// bits 15-5 are undefined | ||
return m_ccr & 0x1f; | ||
} | ||
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void sh2_sh7014_device::ccr_w(offs_t offset, uint16_t data, uint16_t mem_mask) | ||
{ | ||
// bit 0 - CECS0 CS0 Space Cache Enable | ||
// bit 1 - CECS1 CS1 Space Cache Enable | ||
// bit 2 - CECS2 CS2 Space Cache Enable | ||
// bit 3 - CECS3 CS3 Space Cache Enable | ||
// bit 4 - CEDRAM DRAM Space Cache Enable | ||
COMBINE_DATA(&m_ccr); | ||
} |
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// license:BSD-3-Clause | ||
// copyright-holders:windyfairy | ||
/*************************************************************************** | ||
SH-2 SH7014 | ||
***************************************************************************/ | ||
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#ifndef MAME_CPU_SH_SH7014_H | ||
#define MAME_CPU_SH_SH7014_H | ||
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#pragma once | ||
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#include "sh2.h" | ||
#include "sh7014_bsc.h" | ||
#include "sh7014_dmac.h" | ||
#include "sh7014_intc.h" | ||
#include "sh7014_mtu.h" | ||
#include "sh7014_port.h" | ||
#include "sh7014_sci.h" | ||
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class sh2_sh7014_device : public sh2_device | ||
{ | ||
public: | ||
sh2_sh7014_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); | ||
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template<int Sci> auto sci_tx_w() { | ||
return m_sci[Sci].lookup()->write_sci_tx(); | ||
} | ||
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template<int Sci> void sci_set_external_clock_period(const attotime &period) { | ||
m_sci[Sci].lookup()->set_external_clock_period(period); | ||
} | ||
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template<int Sci> void sci_set_send_full_data_transmit_on_sync_hack(bool enabled) { | ||
m_sci[Sci].lookup()->set_send_full_data_transmit_on_sync_hack(enabled); | ||
} | ||
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auto read_porta() { return m_port.lookup()->port_a_read_callback(); } | ||
auto write_porta() { return m_port.lookup()->port_a_write_callback(); } | ||
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auto read_portb() { return m_port.lookup()->port_b_read_callback(); } | ||
auto write_portb() { return m_port.lookup()->port_b_write_callback(); } | ||
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auto read_porte() { return m_port.lookup()->port_e_read_callback(); } | ||
auto write_porte() { return m_port.lookup()->port_e_write_callback(); } | ||
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auto read_portf() { return m_port.lookup()->port_f_read_callback(); } | ||
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protected: | ||
virtual void device_start() override; | ||
virtual void device_reset() override; | ||
virtual void device_add_mconfig(machine_config &config) override; | ||
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virtual void execute_set_input(int inputnum, int state) override; | ||
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virtual void sh2_exception_internal(const char *message, int irqline, int vector) override; | ||
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private: | ||
void sh7014_map(address_map &map); | ||
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void set_irq(int vector, int level, bool is_internal); | ||
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void notify_dma_source(uint32_t source); | ||
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uint16_t ccr_r(); | ||
void ccr_w(offs_t offset, uint16_t dat, uint16_t mem_mask = ~0); | ||
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required_device_array<sh7014_sci_device, 2> m_sci; | ||
required_device<sh7014_bsc_device> m_bsc; | ||
required_device<sh7014_dmac_device> m_dmac; | ||
required_device<sh7014_intc_device> m_intc; | ||
required_device<sh7014_mtu_device> m_mtu; | ||
required_device<sh7014_port_device> m_port; | ||
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devcb_write_line::array<2> m_sci_tx_cb; | ||
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uint16_t m_ccr; | ||
}; | ||
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DECLARE_DEVICE_TYPE(SH2_SH7014, sh2_sh7014_device) | ||
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#endif // MAME_CPU_SH_SH7014_H |
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