machine/s2350.cpp: Add new AMI S2350 USRT, prep for Heath hard-sectored support

[mgarlanger]

Adds the AMI's USRT S2350 USRT needed for the Heath hard-sectored disk controller.

This is prep work for supporting the H-88-1 hard-sectored controller for the Heath H89.

[cuavas]

Can you please make this always log (e.g. with logerror) when the host system uses an unimplemented, like configuring a smaller word size or enabling parity? It helps greatly when hooking a device up to a system if you get a notification when you run into a known limitation.

[cuavas]

K&R formatting snuck in (rest of the file is Allman).

[mgarlanger]

Can you please make this always log (e.g. with logerror) when the host system uses an unimplemented, like configuring a smaller word size or enabling parity? It helps greatly when hooking a device up to a system if you get a notification when you run into a known limitation.

The configuration for things like data size, parity on/off, even/odd, is done by setting the chip's pins high/low:

NDB1/NDB2        39-40       Number Data Bits
NPB                3         No Parity Bit
POE                4         Parity Odd/Even

I didn't define any methods to allow those to be changed. So it is basically hard-coded as NDB1 and NDB2 are set to high (8 bits), NPB is set to high (no parity), and POE is a don't care. If someone wants to use this chip and needs a different configuration, they would need to implement it.

[cuavas]

Can you please make this always log (e.g. with logerror) when the host system uses an unimplemented, like configuring a smaller word size or enabling parity? It helps greatly when hooking a device up to a system if you get a notification when you run into a known limitation.

The configuration for things like data size, parity on/off, even/odd, is done by setting the chip's pins high/low:

NDB1/NDB2        39-40       Number Data Bits
NPB                3         No Parity Bit
POE                4         Parity Odd/Even

I didn't define any methods to allow those to be changed. So it is basically hard-coded as NDB1 and NDB2 are set to high (8 bits), NPB is set to high (no parity), and POE is a don't care. If someone wants to use this chip and needs a different configuration, they would need to implement it.

Ah, so it's not controlled by register writes. That's OK then.