cpu/t11: minor enhancements: #11964
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cpu/t11: minor enhancements: #11964
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Opcode fetch ignores least significant bit of PC; some tests check this. MTPS and MFPS are byte-wide instructions. Define instruction set variants and reject instructions that are invalid for current CPU type.
cuavas
requested changes
Jan 22, 2024
src/devices/cpu/t11/t11ops.hxx
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| /* test if insn is supported by the CPU */ | ||
| #define CHECK_IS(d) if (!(c_insn_set & (d))) { illegal(op); return; } |
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This can produce weird effects if someone does something like:
if (foo)
CHECK_IS(IS_LEIS)
else
bar();To make the macro work more like a single statement, wrap it in a dummy do/while loop:
#define CHECK_IS(d) do { if (!(c_insn_set & (d))) { illegal(op); return; } while (false)
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| #define T11_IRQ0 0 /* IRQ0 */ | ||
| #define T11_IRQ1 1 /* IRQ1 */ | ||
| #define T11_IRQ2 2 /* IRQ2 */ | ||
| #define T11_IRQ3 3 /* IRQ3 */ |
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These input line constants are used in at least src/mame/dec/pdp11.cpp and possibly other places. The code currently doesn’t compile. If you give them a new home (e.g. as static inline constexpr inside t11_device), please do a full build and update everything that uses them.
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I'll update that to use existing enum (t11_device::CP0_LINE)
Mokona
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to Mokona/mame
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Feb 28, 2024
* Ignore least significant bit of PC when fetching opcodes. * Corrected MTPS and MFPS to be byte-wide. * Reject instructions not implemented by each variant.
stonedDiscord
pushed a commit
to stonedDiscord/mame
that referenced
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Apr 8, 2024
* Ignore least significant bit of PC when fetching opcodes. * Corrected MTPS and MFPS to be byte-wide. * Reject instructions not implemented by each variant.
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Opcode fetch ignores least significant bit of PC; some tests check this. MTPS and MFPS are byte-wide instructions.
Define instruction set variants and reject instructions that are invalid for current CPU type.