Hi Zues...

boards/altera-de2-115/syn/kotku.sdc

@@ -50,7 +50,7 @@ derive_clock_uncertainty
 #**************************************************************
 # Set False Path
 #**************************************************************
-set_false_path -from {rst} -hold -rise_to {speaker:speaker|speaker_i2c_av_config:i2c_av_config|mI2C_CTRL_CLK}
+set_false_path -from {reset:reset|rst} -hold -rise_to {speaker:speaker|speaker_i2c_av_config:i2c_av_config|mI2C_CTRL_CLK}
 
 
 #**************************************************************

cores/csrbrg/rtl/csrbrg.v

@@ -20,7 +20,7 @@ module csrbrg(
 	input sys_rst,
 
 	/* WB */
-	input [3:1] wb_adr_i,
+	input [19:1] wb_adr_i,
 	input [15:0] wb_dat_i,
 	output reg [15:0] wb_dat_o,
 	input wb_cyc_i,

cores/flash/flash8_r2.v

@@ -24,7 +24,7 @@ module flash8_r2 (
     input      [15:0] wb_dat_i,
     output reg [15:0] wb_dat_o,
     input             wb_we_i,
-    input             wb_adr_i,
+    input      [19:1] wb_adr_i,
     input      [ 1:0] wb_sel_i,
     input             wb_stb_i,
     input             wb_cyc_i,
@@ -106,7 +106,7 @@ module flash8_r2 (
       address <= 22'h000000;  // Interupt Enable default
     else
       if(wr_command)          // If a write was requested
-        case(wb_adr_i)        // Determine which register was writen to
+        case(wb_adr_i[1])     // Determine which register was writen to
             `FLASH_ALO: address[15: 0] <= wb_dat_i;
             `FLASH_AHI: address[21:16] <= wb_dat_i[5:0];
             default:    ;     // Default

cores/gpio/rtl/hex_display.v

@@ -17,13 +17,17 @@
  */
 
 module hex_display (
-    input  [15:0] num,
+    input  [31:0] num,
     input         en,
 
     output [6:0] hex0,
     output [6:0] hex1,
     output [6:0] hex2,
-    output [6:0] hex3
+    output [6:0] hex3,
+	  output [6:0] hex4,
+    output [6:0] hex5,
+    output [6:0] hex6,
+    output [6:0] hex7
   );
 
   // Module instantiations
@@ -51,4 +55,27 @@ module hex_display (
     .seg (hex3)
   );
 
+  seg_7 hex_group4 (
+    .num (num[19:16]),
+    .en  (en),
+    .seg (hex4)
+  );
+
+  seg_7 hex_group5 (
+    .num (num[23:20]),
+    .en  (en),
+    .seg (hex5)
+  );
+
+  seg_7 hex_group6 (
+    .num (num[27:24]),
+    .en  (en),
+    .seg (hex6)
+  );
+
+  seg_7 hex_group7 (
+    .num (num[31:28]),
+    .en  (en),
+    .seg (hex7)
+  );
 endmodule

cores/gpio/rtl/post.v

@@ -0,0 +1,118 @@
+/*
+ *  Wishbone PostCode Register
+ *  Copyright (C) 2011  Geert Jan Laanstra <g.j.laanstraATutwente.nl>
+ *
+ *  Used for debugging bios startup sequence (see IBM AT technical reference)
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ *
+ *  2011-06-27 Geert Jan Laanstra
+ */
+
+module post (
+  input         wb_clk_i,
+  input         wb_rst_i,
+
+  input         wb_stb_i,
+  input         wb_cyc_i,
+  input  [19:1] wb_adr_i,
+  input         wb_we_i,
+  input  [ 1:0] wb_sel_i,
+  input  [15:0] wb_dat_i,
+  output [15:0] wb_dat_o,
+  output        wb_ack_o,
+
+
+  output [ 7:0] postcode
+  );
+
+  //------------------------------------------------------------------------------------------------------------------
+  // PostCode WB slave
+  //------------------------------------------------------------------------------------------------------------------
+
+  // delay stb
+  reg wb_stb_i_d1;
+  always @ (posedge wb_clk_i)
+    wb_stb_i_d1 <= wb_rst_i ? 1'b0 : wb_stb_i;
+
+  // detect start of access
+  wire wb_stb;
+  assign wb_stb = wb_stb_i & ~wb_stb_i_d1;
+
+  // generate common write or read
+  wire wr;
+  wire rd;
+  assign wr = wb_stb   & wb_cyc_i & wb_we_i  & ~wb_sel_i[1] &  wb_sel_i[0] & ~wb_ack;	 // Allow only byte access
+  assign rd = wb_stb_i & wb_cyc_i & ~wb_we_i & ~wb_sel_i[1] &  wb_sel_i[0] & ~wb_ack;
+
+  // generate write enables
+  reg wr_post;
+  always @(posedge wb_clk_i)
+    begin
+      wr_post <= wb_rst_i ? 1'b0 : wr;
+    end
+
+  // store data for pipeline block write support
+  reg [15:0] wb_dat_ir;
+  always @(posedge wb_clk_i)
+  begin
+    if (wb_rst_i)
+      wb_dat_ir <= 16'h0000;
+    else
+      wb_dat_ir <= wb_dat_i;
+  end
+
+  reg [7:0] post;
+
+  always @(posedge wb_clk_i)
+    begin
+	    if (wb_rst_i)
+		    begin
+			  post <= 8'b0;
+			end
+	    else
+		    begin
+			  post = wr_post ? wb_dat_ir[ 7:0] : post;
+		    end
+    end
+
+  // reading status
+  reg [15:0] dat_o;
+  always @(posedge wb_clk_i)
+    begin
+      // reading imr
+	  if (wb_rst_i)
+      dat_o[15:8] <= 8'h00;
+    else
+      dat_o[15:8] <= 8'h00;
+
+      // reading of register
+	  if (wb_rst_i)
+	    dat_o[ 7:0] <= 8'h00;
+    else if (rd)
+      dat_o[ 7:0] <= post;
+    else
+      dat_o[7:0] <= 8'h00;	  
+    end
+  assign wb_dat_o = dat_o;
+
+  // acknowledge back to wb
+  reg wb_ack;
+  always @(posedge wb_clk_i)
+    wb_ack <= wb_rst_i ? 1'b0 : ((wr | rd) & ~wb_ack);
+  assign wb_ack_o = wb_ack;
+
+  assign postcode = post;
+endmodule

cores/gpio/rtl/sw_leds.v

@@ -21,7 +21,7 @@ module sw_leds (
     // Wishbone slave interface
     input         wb_clk_i,
     input         wb_rst_i,
-    input         wb_adr_i,
+    input  [19:1] wb_adr_i,
     output [15:0] wb_dat_o,
     input  [15:0] wb_dat_i,
     input  [ 1:0] wb_sel_i,
@@ -48,13 +48,13 @@ module sw_leds (
   // Continuous assignments
   assign op       = wb_cyc_i & wb_stb_i;
   assign wb_ack_o = op;
-  assign wb_dat_o = wb_adr_i ? { 2'b00, leds_ }
-                             : { 8'h00, sw_ };
+  assign wb_dat_o = wb_adr_i[1] ? { 2'b00, leds_ }
+                                : { 8'h00, sw_   };
 
   // Behaviour
   always @(posedge wb_clk_i)
     leds_ <= wb_rst_i ? 14'h0
-      : ((op & wb_we_i & wb_adr_i) ? wb_dat_i[13:0] : leds_);
+      : ((op & wb_we_i & wb_adr_i[1]) ? wb_dat_i[13:0] : leds_);
 
   always @(posedge wb_clk_i)
   begin