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[EraVM][MC] Refine the definitions of ret-like instructions #567
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@sayon @akiramenai Please check that this patch models the spec correctly. |
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Undone changes a bit to merge as much as possible before renaming the mnemonics:
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Benchmark results:
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The implementation LGTM, thanks.
@sayon could you double check the constraint on ret-like input with the spec?
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The constraints LGTM. Question: for the disassembler, will the non-sensical variants like |
@sayon Instructions like On the other hand, maybe defining all 24 variants of NOP was too permissive - but it is encoded very similar to other arithmetic instructions (except for not having the Considering the nonsensical-ness of |
The question seems to boil down to the following: what happens if an instruction with the opcode set to 1070 (
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It is statically impossible to distinguish between emitted far returns and near returns. A third party may forge an instruction like Here we write that the semantic is decided in runtime; please tell me if it is not clear and I will try to rework/reformulate/make it more visible. |
+1 to @sayon. It sounds like it makes sense to emit an error if to assemble |
If this is a problem, we may allow to assemble |
Make R1 register be understood as the default operand of `RETrl` and `REVERTrl` instructions (but make this alias non-default for printing until switched to the new asm syntax). Change panic instruction to either accept jump target operand or none at all.
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Updated the patch and the description. Now instructions like Until switching to the new syntax, the aliases for "
After switching to the new syntax and removing
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Make R1 register be understood as the default operand of
RETrl
andREVERTrl
instructions (but make this alias non-default for printinguntil switched to the new asm syntax).
Change panic instruction to either accept jump target operand
or none at all.