Fix PCIE configuration issue on LeafHill

The PCIe root ports configurations are not correct in the CFGDATA for LeafHill/OxbowHill/JuniperHill/UP2. This patch fixed the root ports configurations properly. It also enabled Windows 10 installation on Leafhill. It fixed slimbootloader#93 . Signed-off-by: Maurice Ma <maurice.ma@intel.com>
mauricema · Feb 13, 2019 · 7b50aef · 7b50aef
1 parent d7ec54a
commit 7b50aef
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Showing 3 changed files with 15 additions and 8 deletions.
diff --git a/Platform/ApollolakeBoardPkg/CfgData/CfgData_Ext_Gpmrb.dlt b/Platform/ApollolakeBoardPkg/CfgData/CfgData_Ext_Gpmrb.dlt
@@ -37,7 +37,7 @@ MEMORY_CFG_DATA.Ch1_Bit_swizzling        | { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
 MEMORY_CFG_DATA.Ch2_Bit_swizzling        | { 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17 }
 MEMORY_CFG_DATA.Ch3_Bit_swizzling        | { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F }
 PCIE_RP_CFG_DATA.PcieRpFeatures1.En            | 0
-PCIE_RP_CFG_DATA.PcieRpFeatures3.En            | 0
+PCIE_RP_CFG_DATA.PcieRpFeatures3.En            | 1
 PCIE_RP_CFG_DATA.PcieRpFeatures3.ClkReqSup     | 0
 PCIE_RP_CFG_DATA.PcieRpFeatures5.ClkReqSup     | 0
 PCIE_RP_CFG_DATA.PcieRpFeatures0.ClkReqNum     | 2

diff --git a/Platform/ApollolakeBoardPkg/CfgData/CfgData_Ext_Up2.dlt b/Platform/ApollolakeBoardPkg/CfgData/CfgData_Ext_Up2.dlt
@@ -36,4 +36,11 @@ MEMORY_CFG_DATA.Ch0_Bit_swizzling        | { 0xD,	0xA,	0x8,	0xB,	0xC,	0xF,	0xE,
 MEMORY_CFG_DATA.Ch1_Bit_swizzling        | { 0x0,	0x7,	0x4,	0x5,	0x6,	0x2,	0x3,	0x1,	0x8,	0xF,	0xD,	0xB,	0xA,	0x9,	0xE,	0xC,	0x17,	0x11,	0x13,	0x12,	0x14,	0x15,	0x16,	0x10,	0x1C,	0x1A,	0x1D,	0x1F,	0x18,	0x19,	0x1E,	0x1B }
 MEMORY_CFG_DATA.Ch2_Bit_swizzling        | { 0xD,	0x8,	0xB,	0xE,	0xC,	0xF,	0x9,	0xA,	0x4,	0x7,	0x1,	0x6,	0x2,	0x3,	0x0,	0x5,	0x18,	0x19,	0x1C,	0x1A,	0x1D,	0x1E,	0x1F,	0x1B,	0x11,	0x13,	0x15,	0x10,	0x16,	0x12,	0x17,	0x14 }
 MEMORY_CFG_DATA.Ch3_Bit_swizzling        | { 0x0,	0x5,	0x4,	0x7,	0x3,	0x2,	0x6,	0x1,	0xA,	0xB,	0x8,	0x9,	0xC,	0xE,	0xD,	0xF,	0x12,	0x16,	0x14,	0x13,	0x17,	0x11,	0x15,	0x10,	0x19,	0x1F,	0x1D,	0x1B,	0x1E,	0x18,	0x1C,	0x1A }
-DEV_EN_CFG_DATA.DevEnControl1.SdcardEnable    | 0x0
+DEV_EN_CFG_DATA.DevEnControl1.SdcardEnable    | 0x0
+
+PCIE_RP_CFG_DATA.PcieRpFeatures0.En      | 0x0
+PCIE_RP_CFG_DATA.PcieRpFeatures1.En      | 0x0
+PCIE_RP_CFG_DATA.PcieRpFeatures3.En      | 0x1
+PCIE_RP_CFG_DATA.PcieRpFeatures5.En      | 0x1
+PCIE_RP_CFG_DATA.PcieRpFeatures2.ClkReqNum | 0x0
+PCIE_RP_CFG_DATA.PcieRpFeatures4.ClkReqNum | 0x2
diff --git a/Platform/ApollolakeBoardPkg/CfgData/CfgData_PcieRp.dsc b/Platform/ApollolakeBoardPkg/CfgData/CfgData_PcieRp.dsc
@@ -25,12 +25,12 @@
 
   # !HDR EMBED:{PCIE_RP_CFG_DATA:TAG_302:START}
 
-  # !BSF SUBT:{PCIERP_TMPL:0 : 0x93}
-  # !BSF SUBT:{PCIERP_TMPL:1 : 0x97}
-  # !BSF SUBT:{PCIERP_TMPL:2 : 0x83}
-  # !BSF SUBT:{PCIERP_TMPL:3 : 0x87}
-  # !BSF SUBT:{PCIERP_TMPL:4 : 0x8B}
-  # !BSF SUBT:{PCIERP_TMPL:5 : 0x8F}
+  # !BSF SUBT:{PCIERP_TMPL:0 : 0x8B}
+  # !BSF SUBT:{PCIERP_TMPL:1 : 0x8F}
+  # !BSF SUBT:{PCIERP_TMPL:2 : 0x87}
+  # !BSF SUBT:{PCIERP_TMPL:3 : 0x86}
+  # !BSF SUBT:{PCIERP_TMPL:4 : 0x83}
+  # !BSF SUBT:{PCIERP_TMPL:5 : 0x8E}
 
   #                                      Power       : Reset
   # !BSF SUBT:{PCIERP_CTRL_PIN_TMPL:0 :  0x0021318A  : 0x0021618E}