ezPort
ezPort setup for flasing rig which uses two mchck devices is deescibed in blog post MC HCK Flashing Rig
- MCU pinout source http://cache.freescale.com/files/32bit/doc/data_sheet/K20P48M50SF0.pdf
- ezPort description, chapter 29, http://cache.freescale.com/files/32bit/doc/ref_manual/K20P48M50SF0RM.pdf
| MCU | silk | MCHCK | ezPort | Bus Pirate |
|---|---|---|---|---|
| PTA0 | SWD CK | SWD_CLK | EZP_CK | CLK |
| PTA1 | A1 | PL4 | EZP_DI | MOSI |
| PTA2 | A2 | PL5 | EZP_DO | MISO |
| PTA4 | A4 | PL6 | EZP_CS | CS |
6.4.2 EzPort Switching Specifications, Table 22:
| Num | Description | Min. | Max. | Unit |
|---|---|---|---|---|
| Operating voltage | 1.71 | 3.6 | V | |
| EP1 | EZP_CK frequency of operation (all commands except READ) | - | fSYS/2 | MHz |
| EP1a | EZP_CK frequency of operation (READ command) | - | fSYS/8 | MHz |
| EP2 | EZP_CS negation to next EZP_CS assertion | 2 * tEZP_CK | - | ns |
| EP3 | EZP_CS input valid to EZP_CK high (setup) | 5 | - | ns |
| EP4 | EZP_CK high to EZP_CS input invalid (hold) | 5 | - | ns |
| EP5 | EZP_D input valid to EZP_CK high (setup) | 2 | - | ns |
| EP6 | EZP_CK high to EZP_D input invalid (hold) | 5 | - | ns |
| EP7 | EZP_CK low to EZP_Q output valid | - | 17 | ns |
| EP8 | EZP_CK low to EZP_Q output invalid (hold) | 0 | - | ns |
| EP9 | EZP_CS negation to EZP_Q tri-state | - | 12 | ns |
dpavlin@blue:/blue-zfs/mchck$ ~/bin/bp.sh + microcom -p /dev/serial/by-id/usb-FTDI_FT232R_USB_UART_AE01J55Q-if00-port0 connected to /dev/serial/by-id/usb-FTDI_FT232R_USB_UART_AE01J55Q-if00-port0 Escape character: Ctrl-\ Type the escape character followed by c to get to the menu or q to quit HiZ>v Pinstates: 1.(BR) 2.(RD) 3.(OR) 4.(YW) 5.(GN) 6.(BL) 7.(PU) 8.(GR) 9.(WT) 0.(Blk) GND 3.3V 5.0V ADC VPU AUX CLK MOSI CS MISO P P P I I I I I I I GND 0.00V 0.00V 0.00V 0.00V L L L L L
HiZ> m 5 1 1 2 1 2 2 SPI (spd ckp ske smp csl hiz)=( 1 0 1 0 1 0 ) Ready
SPI>[ /CS ENABLED
SPI>W POWER SUPPLIES ON
SPI>] /CS DISABLED
SPI>[0x05 r] /CS ENABLED WRITE: 0x05 READ: 0x00 /CS DISABLED
SPI>[0x05 r] /CS ENABLED WRITE: 0x05 READ: 0x80 /CS DISABLED
SPI>[0x06] /CS ENABLED WRITE: 0x06 /CS DISABLED
SPI>[0x05 r] /CS ENABLED WRITE: 0x05 READ: 0x82 /CS DISABLED
SPI>[0xc7] /CS ENABLED WRITE: 0xC7 /CS DISABLED
SPI>[0x05 r] /CS ENABLED WRITE: 0x05 READ: 0x00 /CS DISABLED
SPI>[0xB9] /CS ENABLED WRITE: 0xB9 /CS DISABLED