VLSI 1 Final Project by Michael Ebenstein (control_cell) and Ian SymSmith (compute_tile)
For a detailed explanation see our report.
- Place you instructions and initial memory blocks in the
projectdata/images
folder, and replaceprogram.data
andweights.data
respectively. - Compile the design
module load synopsys/2018
vcs -full64 -f cmd_fl -debug
- Launch the simulator
./simv -gui &