VLSI 1 Final Project by Michael Ebenstein (control_cell) and Ian SymSmith (compute_tile)
For a detailed explanation see our report.
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- Place you instructions and initial memory blocks in the
projectdata/imagesfolder, and replaceprogram.dataandweights.datarespectively. - Compile the design
module load synopsys/2018
vcs -full64 -f cmd_fl -debug- Launch the simulator
./simv -gui &






