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Repository for my VLSI I final project. We build a naive ML processor in Verilog and simulated and synthesised it using Cadence Tools.

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A Naive Machine Learning Processor

VLSI 1 Final Project by Michael Ebenstein (control_cell) and Ian SymSmith (compute_tile)

For a detailed explanation see our report.

Instructions

  1. Place you instructions and initial memory blocks in the projectdata/images folder, and replace program.data and weights.data respectively.
  2. Compile the design
module load synopsys/2018
vcs -full64 -f cmd_fl -debug
  1. Launch the simulator
./simv -gui &

Results

Addition

ReLU

Convolution

Max-Pooling

Matrix-multiplication

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Repository for my VLSI I final project. We build a naive ML processor in Verilog and simulated and synthesised it using Cadence Tools.

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