Mips Processor with Pipeline

Verilog Code to simulate MIPS Processor with pipeline.

Developed as the course project for Computer Architecture Course @ German University in Cairo.

How to Run

1 - Download the verilog compiler http://iverilog.icarus.com/

2 - Clone this repo

git clone https://github.com/melzareix/mips-pipeline.git
cd mips-pipeline

3 - Compile all the files

iverilog -o main *.v

4 - Run the compiled binary

vvp main

Name		Name	Last commit message	Last commit date
Latest commit History 9 Commits
ALU.v		ALU.v
ALUControl.v		ALUControl.v
ALUControl_tb.v		ALUControl_tb.v
ALU_tb.v		ALU_tb.v
EX_MEM.v		EX_MEM.v
ID_EX.v		ID_EX.v
IF_ID.v		IF_ID.v
LICENSE		LICENSE
MEM_WB.v		MEM_WB.v
Processor.v		Processor.v
Processor_tb.v		Processor_tb.v
README.md		README.md
controlUnit.v		controlUnit.v
controlUnit_tb.v		controlUnit_tb.v
dataMemory.v		dataMemory.v
dataMemory_tb.v		dataMemory_tb.v
inst_mem.v		inst_mem.v
inst_mem_tb.v		inst_mem_tb.v
main		main
regFile.v		regFile.v
regfile_tb.v		regfile_tb.v