A real KICKSTART

There are many ways - if you have your own preferred tools and methods use them.

TIP: Before you do any own coding look at picorv32 it does not pass all contest requirements includes however lots of goodies!

Step 1: Compiling RISCV sources to run on the SoftCPU

You can skip this fully for the first start, and grab ready made images

https://github.com/micro-FPGA/engine-V-simulator/tree/master/Win32/Debug/images

Not setting up GCC, not fetching sources, no zephyr setup.

Skipped.

You may have to-do recompile the applications yourself, but you can do it later in the design cycle.

Step 2A: HDL Coding, simulation and FPGA verification (Vivado)

If you have previous Vivado experience, grab some Xilinx 7 Series board, if not go to Step 2B

Any 7 series board would actually do, whatever you have (as long as it has JTAG)

Start Vivado, create new project, add your verilog files, create new Block Design, add your verilog as RTL module, and wire up simulation clock generator.

Now create another Block Design and add your verilog as RTL as module, add VIO to control the reset of your CPU and ILA as Logic Analyzer

Compile to bitstream, download and arm the Logic Analyzer

SPI Bootloader sending SPI read instruction to external SPI Flash to read RISCV code from offset 0x200000

You are done with simulation and FPGA verification setup. Go write and debug your HDL !

Step 2B: HDL Coding, simulation and FPGA verification (everyone)

Setup your favorite simulator or use verilator or use simulator from Libero or Radiant.

Try to minimize the time you need to use FPGA debugging with Identify or Reveal, better simulate more.

Step 3: Testing on Contest Platform (Microsemi/Lattice)

• RV32I test binaries from step 1
• verilog code from 2
• add in TOP.V connection from program counter bit 11 to output port DEBUG_LED
• compile with Libero and Radiant and assign the DEBUG_LED to real LED

When you program the target boards using the RV32I Compliance test binaries the LED would show PASS/FAIL

Lattice/Radiant

Setting up for Radiant is very easy, create new project, add verilog files, then in Device Constraint editor (for MDP board device U3 FPGA - C)

LED is connected to single LED, using the RGB led would need a special primitive that would not simulate in verilator so it easier to use the single one (no need to take special care about verilator compatibility).

Then:

• J23 set jumper to 2-3
• J26 move jumper to 1,2
• J27 move one jumper to 9,10 leave other open
• J28 open all jumpers
• change prog mode jumpers to iCE (horizontal)
• set demo switch: S1 OFF, S2 ON

Press green Arrow button in Radiant Programmer and check the LED.

Microsemi/Libero

With Microsemi SmartFusion2/IGLOO2 a program bootstrap solution is needed to test on the real boards. You can initialize the LSRAM only for the Libero Simulator.

More about the boot ROM options in SoC Design

todo

Step 4: Dhrystone/Zephyr testing

• RV32I test binaries from step 1
• verilog code from 2

You can run Dhrystone and Zephyr apps without having the UART peripheral with Verilator, is actually very easy to setup.

Step 5:

This is where hard work begins

• UART peripheral, or bit-bang UART firmware
• Testing of the Interrupts/Timer
• Bootloader
• Optimization for smaller size
• Optimization for Fmax in FPGA
• Scripts and and utilities
• Documentation and packaging