Fastest Design

Only Dhrystones per Second metrics is used so the design must minimize CPI (Clocks per Instruction) and maximize computing performance and achieve high clock rate on the selected targets!

You must figure out during the development from FPGA tool reports the maximum Clock you can achieve, then adjust PLL to produce that clock and test the design is running on the board. Then you take that clock value and use as HZ parameter when compiling the Dhrystone code, after that you take this updated Dhrystone test and use it to create the final FPGA images.

More about Dhrystone test

Lattice UP5K

Hint: use the DSP blocks to the max, maybe it is possible to even implement RV32IM

You must use a bootstrap to load code over UART or from SPI into SPRAM, XiP from SPI is way too slow.

Microsemi

For fastest design the code and data must be in FPGA RAM made of LSRAM blocks (all code+data fits into LSRAM), eNVM/eSRAM can not be used, all code most be copied from eNVM to local LSRAM, this can be done by a bootstrap, by some FSM or with Cortex-M3 assisted boot (in that case Cortex-M3 would copy code from eNVM into LSRAM block muxed to FIC port durint pre-boot of the RISCV CPU). More in Soc Design

RV32IM should be implemented not RV32I.

You could over-clock MicroSemi FPGA a lot when you run the board at -40C ambient. However the judges would unlikely be very happy if you write in your contest entry documentation that the Dhrystone test must be done in climate chamber.