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stm32: Add support for STM32L1 MCUs.
This change adds STM32L1 support to the STM32 port.
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,117 @@ | ||
| Port,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15, | ||
| ,,SYS_AF,TIM2,TIM3/TIM4/TIM5,TIM9/TIM10/TIM11,I2C1/I2C2,SPI1/SPI2,SPI3,USART1/USART2/USART3,UART4/UART5,,,,,,,,ADC | ||
| PortA,PA0,,TIM2_CH1_ETR,TIM5_CH1,,,,,USART2_CTS,,,,,,,,EVENTOUT,ADC1_IN0 | ||
| PortA,PA1,,TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,,,,,,,,EVENTOUT,ADC1_IN1 | ||
| PortA,PA2,,TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,,,,,,,,EVENTOUT,ADC1_IN2 | ||
| PortA,PA3,,TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,,,,,,EVENTOUT,ADC1_IN3 | ||
| PortA,PA4,,,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,,EVENTOUT,ADC1_IN4 | ||
| PortA,PA5,,TIM2_CH1_ETR,,,,SPI1_SCK,,,,,,,,,,EVENTOUT,ADC1_IN5 | ||
| PortA,PA6,,,TIM3_CH1,TIM10_CH1,,SPI1_MISO,,,,,,,,,,EVENTOUT,ADC1_IN6 | ||
| PortA,PA7,,,TIM3_CH2,TIM11_CH1,,SPI1_MOSI,,,,,,,,,,EVENTOUT,ADC1_IN7 | ||
| PortA,PA8,MCO,,,,,,,USART1_CK,,,,,,,,EVENTOUT, | ||
| PortA,PA9,,,,,,,,USART1_TX,,,,,,,,EVENTOUT, | ||
| PortA,PA10,,,,,,,,USART1_RX,,,,,,,,EVENTOUT, | ||
| PortA,PA11,,,,,,SPI1_MISO,,USART1_CTS,,,,,,,,EVENTOUT, | ||
| PortA,PA12,,,,,,SPI1_MOSI,,USART1_RTS,,,,,,,,EVENTOUT, | ||
| PortA,PA13,JTMS/SWDIO,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortA,PA14,JTCK/SWCLK,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortA,PA15,JTDI,TIM2_CH1_ETR,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,,,,,,,,,EVENTOUT, | ||
| PortB,PB0,,,TIM3_CH3,,,,,,,,,,,,,EVENTOUT,ADC1_IN8 | ||
| PortB,PB1,,,TIM3_CH4,,,,,,,,,,,,,EVENTOUT,ADC1_IN9 | ||
| PortB,PB2,BOOT1,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortB,PB3,JTDO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK/I2S3_CK,,,,,,,,,EVENTOUT, | ||
| PortB,PB4,NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,,,,,,,,,EVENTOUT, | ||
| PortB,PB5,,,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,,,,,,,,,EVENTOUT, | ||
| PortB,PB6,,,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT, | ||
| PortB,PB7,,,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,,,,EVENTOUT, | ||
| PortB,PB8,,,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,,,,,,,EVENTOUT, | ||
| PortB,PB9,,,TIM4_CH4,TIM11_CH1,I2C1_SDA,,,,,,,,,,,EVENTOUT, | ||
| PortB,PB10,,TIM2_CH3,,,I2C2_SCL,,,USART3_TX,,,,,,,,EVENTOUT, | ||
| PortB,PB11,,TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,,,,,,EVENTOUT, | ||
| PortB,PB12,,,,TIM10_CH1,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,,,,,,,,EVENTOUT,ADC1_IN18 | ||
| PortB,PB13,,,,TIM9_CH1,,SPI2_SCK/I2S2_CK,,USART3_CTS,,,,,,,,EVENTOUT,ADC1_IN19 | ||
| PortB,PB14,,,,TIM9_CH2,,SPI2_MISO,,USART3_RTS,,,,,,,,EVENTOUT,ADC1_IN20 | ||
| PortB,PB15,,,,TIM11_CH1,,SPI2_MOSI/I2S2_SD,,,,,,,,,,EVENTOUT,ADC1_IN21 | ||
| PortC,PC0,,,,,,,,,,,,,,,,EVENTOUT,ADC1_IN10 | ||
| PortC,PC1,,,,,,,,,,,,,,,,EVENTOUT,ADC1_IN11 | ||
| PortC,PC2,,,,,,,,,,,,,,,,EVENTOUT,ADC1_IN12 | ||
| PortC,PC3,,,,,,,,,,,,,,,,EVENTOUT,ADC1_IN13 | ||
| PortC,PC4,,,,,,,,,,,,,,,,EVENTOUT,ADC1_IN14 | ||
| PortC,PC5,,,,,,,,,,,,,,,,EVENTOUT,ADC1_IN15 | ||
| PortC,PC6,,,TIM3_CH1,,,I2S2_MCK,,,,,,,,,,EVENTOUT, | ||
| PortC,PC7,,,TIM3_CH2,,,,I2S3_MCK,,,,,,,,,EVENTOUT, | ||
| PortC,PC8,,,TIM3_CH3,,,,,,,,,,,,,EVENTOUT, | ||
| PortC,PC9,,,TIM3_CH4,,,,,,,,,,,,,EVENTOUT, | ||
| PortC,PC10,,,,,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,,,,,,,EVENTOUT, | ||
| PortC,PC11,,,,,,,SPI3_MISO,USART3_RX,UART4_RX,,,,,,,EVENTOUT, | ||
| PortC,PC12,,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,,,,EVENTOUT, | ||
| PortC,PC13,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortC,PC14,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortC,PC15,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortD,PD0,,,,TIM9_CH1,,SPI2_NSS/I2S2_WS,,,,,,,,,,EVENTOUT, | ||
| PortD,PD1,,,,,,SPI2_SCK/I2S2_CK,,,,,,,,,,EVENTOUT, | ||
| PortD,PD2,,,TIM3_ETR,,,,,,UART5_RX,,,,,,,EVENTOUT, | ||
| PortD,PD3,,,,,,SPI2_MISO,,USART2_CTS,,,,,,,,EVENTOUT, | ||
| PortD,PD4,,,,,,SPI2_MOSI/I2S2_SD,,USART2_RTS,,,,,,,,EVENTOUT, | ||
| PortD,PD5,,,,,,,,USART2_TX,,,,,,,,EVENTOUT, | ||
| PortD,PD6,,,,,,,,USART2_RX,,,,,,,,EVENTOUT, | ||
| PortD,PD7,,,,TIM9_CH2,,,,USART2_CK,,,,,,,,EVENTOUT, | ||
| PortD,PD8,,,,,,,,USART3_TX,,,,,,,,EVENTOUT, | ||
| PortD,PD9,,,,,,,,USART3_RX,,,,,,,,EVENTOUT, | ||
| PortD,PD10,,,,,,,,USART3_CK,,,,,,,,EVENTOUT, | ||
| PortD,PD11,,,,,,,,USART3_CTS,,,,,,,,EVENTOUT, | ||
| PortD,PD12,,,TIM4_CH1,,,,,USART3_RTS,,,,,,,,EVENTOUT, | ||
| PortD,PD13,,,TIM4_CH2,,,,,,,,,,,,,EVENTOUT, | ||
| PortD,PD14,,,TIM4_CH3,,,,,,,,,,,,,EVENTOUT, | ||
| PortD,PD15,,,TIM4_CH4,,,,,,,,,,,,,EVENTOUT, | ||
| PortE,PE0,,,TIM4_ETR,TIM10_CH1,,,,,,,,,,,,EVENTOUT, | ||
| PortE,PE1,,,,TIM11_CH1,,,,,,,,,,,,EVENTOUT, | ||
| PortE,PE2,TRACECK,,TIM3_ETR,,,,,,,,,,,,,EVENTOUT, | ||
| PortE,PE3,TRACED0,,TIM3_CH1,,,,,,,,,,,,,EVENTOUT, | ||
| PortE,PE4,TRACED1,,TIM3_CH2,,,,,,,,,,,,,EVENTOUT, | ||
| PortE,PE5,TRACED2,,,TIM9_CH1,,,,,,,,,,,,EVENTOUT, | ||
| PortE,PE6,TRACED3,,,TIM9_CH2,,,,,,,,,,,,EVENTOUT, | ||
| PortE,PE7,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortE,PE8,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortE,PE9,,TIM2_CH1_ETR,,,,,,,,,,,,,,EVENTOUT, | ||
| PortE,PE10,,TIM2_CH2,,,,,,,,,,,,,,EVENTOUT, | ||
| PortE,PE11,,TIM2_CH3,,,,,,,,,,,,,,EVENTOUT, | ||
| PortE,PE12,,TIM2_CH4,,,,SPI1_NSS,,,,,,,,,,EVENTOUT, | ||
| PortE,PE13,,,,,,SPI1_SCK,,,,,,,,,,EVENTOUT, | ||
| PortE,PE14,,,,,,SPI1_MISO,,,,,,,,,,EVENTOUT, | ||
| PortE,PE15,,,,,,SPI1_MOSI,,,,,,,,,,EVENTOUT, | ||
| PortF,PF0,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortF,PF1,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortF,PF2,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortF,PF3,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortF,PF4,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortF,PF5,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortF,PF6,,,TIM5_ETR,,,,,,,,,,,,,EVENTOUT, | ||
| PortF,PF7,,,TIM5_CH2,,,,,,,,,,,,,EVENTOUT, | ||
| PortF,PF8,,,TIM5_CH3,,,,,,,,,,,,,EVENTOUT, | ||
| PortF,PF9,,,TIM5_CH4,,,,,,,,,,,,,EVENTOUT, | ||
| PortF,PF10,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortF,PF11,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortF,PF12,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortF,PF13,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortF,PF14,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortF,PF15,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortG,PG0,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortG,PG1,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortG,PG2,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortG,PG3,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortG,PG4,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortG,PG5,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortG,PG6,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortG,PG7,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortG,PG8,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortG,PG9,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortG,PG10,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortG,PG11,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortG,PG12,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortG,PG13,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortG,PG14,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortG,PG15,,,,,,,,,,,,,,,,EVENTOUT, | ||
| PortH,PH0,,,,,,,,,,,,,,,,, | ||
| PortH,PH1,,,,,,,,,,,,,,,,, | ||
| PortH,PH2,,,,,,,,,,,,,,,,, |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,37 @@ | ||
| /* | ||
| GNU linker script for STM32L152xE | ||
| */ | ||
|
|
||
| /* Specify the memory areas */ | ||
| MEMORY | ||
| { | ||
| FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K /* entire flash */ | ||
| FLASH_FS (rx) : ORIGIN = 0x08064000, LENGTH = 112K /* sectors 100-127 */ | ||
| RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 81408 | ||
| FS_CACHE (xrw) : ORIGIN = 0x20013e00, LENGTH = 512 | ||
| } | ||
|
|
||
| /* produce a link error if there is not this amount of RAM for these sections */ | ||
| _minimum_stack_size = 2K; | ||
| _minimum_heap_size = 16K; | ||
|
|
||
| /* RAM extents for the garbage collector */ | ||
| _ram_start = ORIGIN(RAM); | ||
| _ram_end = ORIGIN(RAM) + LENGTH(RAM); | ||
|
|
||
| /* Define the stack. The stack is full descending so begins just above last byte | ||
| of RAM. Note that EABI requires the stack to be 8-byte aligned for a call. */ | ||
| _estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve; | ||
| _sstack = _estack - 16K; /* tunable */ | ||
|
|
||
| /* RAM extents for the garbage collector */ | ||
| _ram_start = ORIGIN(RAM); | ||
| _ram_end = ORIGIN(RAM) + LENGTH(RAM); | ||
| _heap_start = _ebss; /* heap starts just after statically allocated memory */ | ||
| _heap_end = _sstack; | ||
|
|
||
| /* Filesystem cache in RAM, and storage in flash */ | ||
| _micropy_hw_internal_flash_storage_ram_cache_start = ORIGIN(FS_CACHE); | ||
| _micropy_hw_internal_flash_storage_ram_cache_end = ORIGIN(FS_CACHE) + LENGTH(FS_CACHE); | ||
| _micropy_hw_internal_flash_storage_start = ORIGIN(FLASH_FS); | ||
| _micropy_hw_internal_flash_storage_end = ORIGIN(FLASH_FS) + LENGTH(FLASH_FS); |
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