samd/mcu: Rework the comments in clock_config.c.

For more clarity. clock_config.c is not overly readable, so comments are important.
micropython · Feb 21, 2023 · 60ab556 · 60ab556
1 parent c3afafd
commit 60ab556
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Showing 2 changed files with 25 additions and 16 deletions.
diff --git a/ports/samd/mcu/samd21/clock_config.c b/ports/samd/mcu/samd21/clock_config.c
@@ -135,13 +135,18 @@ void init_clocks(uint32_t cpu_freq) {
     dfll48m_calibration = 0; // please the compiler
 
     // SAMD21 Clock settings
-    // GCLK0: 48MHz from DFLL open loop mode or closed loop mode from 32k Crystal
-    // GCLK1: 32768 Hz from 32K ULP or DFLL48M
-    // GCLK2: 48MHz from DFLL for Peripherals
-    // GCLK3: 1Mhz for the us-counter (TC4/TC5)
-    // GCLK4: 32kHz from crystal, if present
-    // GCLK5: 48MHz from DFLL for USB
-    // GCLK8: 1kHz clock for WDT and RTC
+    //
+    // GCLK0: 48MHz, source: DFLL48M, usage: CPU
+    // GCLK1: 32kHz, source: XOSC32K or OSCULP32K or DFLL48M, usage: FDPLL96M reference
+    // GCLK2: 1-48MHz, source: DFLL48M, usage: Peripherals
+    // GCLK3: 1Mhz,  source: DFLL48M, usage: us-counter (TC4/TC5)
+    // GCLK4: 32kHz, source: XOSC32K, if crystal present, usage: DFLL48M reference
+    // GCLK5: 48MHz, source: DFLL48M, usage: USB
+    // GCLK8: 1kHz,  source: XOSC32K or OSCULP32K, usage: WDT and RTC
+    // DFLL48M: Reference sources:
+    //          - in closed loop mode: eiter XOSC32K or OSCULP32K or USB clock
+    //          - in open loop mode: None
+    // FDPLL96M: Not used (yet). Option to use it for the CPU clock.
 
     NVMCTRL->CTRLB.bit.MANW = 1; // errata "Spurious Writes"
     NVMCTRL->CTRLB.bit.RWS = 1; // 1 read wait state for 48MHz
@@ -169,14 +174,14 @@ void init_clocks(uint32_t cpu_freq) {
     while (GCLK->STATUS.bit.SYNCBUSY) {
     }
 
-    // Connect the GCLK4 to OSC32K via GCLK1 to the DFLL input and for further use.
+    // Connect the GCLK4 to OSC32K
     GCLK->GENDIV.reg = GCLK_GENDIV_ID(4) | GCLK_GENDIV_DIV(1);
     GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_XOSC32K | GCLK_GENCTRL_ID(4);
+    // Connect GCLK4 to the DFLL input.
+    GCLK->CLKCTRL.reg = GCLK_CLKCTRL_GEN_GCLK4 | GCLK_CLKCTRL_ID_DFLL48 | GCLK_CLKCTRL_CLKEN;
     while (GCLK->STATUS.bit.SYNCBUSY) {
     }
 
-    // Connect GCLK4 to the DFLL input and for further use.
-    GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_DFLL48 | GCLK_CLKCTRL_GEN_GCLK4 | GCLK_CLKCTRL_CLKEN;
     // Enable access to the DFLLCTRL reg acc. to Errata 1.2.1
     SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
     while (SYSCTRL->PCLKSR.bit.DFLLRDY == 0) {

diff --git a/ports/samd/mcu/samd51/clock_config.c b/ports/samd/mcu/samd51/clock_config.c
@@ -187,12 +187,16 @@ void init_clocks(uint32_t cpu_freq) {
     dfll48m_calibration = 0; // please the compiler
 
     // SAMD51 clock settings
-    // GCLK0: 48MHz from DFLL48M or 48 - 200 MHz from DPLL0 (SAMD51)
-    // GCLK1: 32768 Hz from 32KULP or DFLL48M
-    // GCLK2: 8-48MHz from DFLL48M for Peripheral devices
-    // GCLK3: 16Mhz for the us-counter (TC0/TC1)
-    // GCLK4: 32kHz from crystal, if present
-    // GCLK5: 48MHz from DFLL48M for USB
+    //
+    // GCLK0: 48MHz, source: 48 - 200 MHz from DPLL0, usage: CPU
+    // GCLK1: 32kHz, source: OSCULP32K or DFLL48M, usage: ref_clk DPLL0
+    // GCLK2: 1-48MHz, source:DFLL48M, usage: Peripheral devices
+    // GCLK3: 16Mhz, source: DLLL48M, usage: us-counter (TC0/TC1)
+    // GCLK4: 32kHz, source: XOSC32K, if crystal present, usage: DFLL48M reference
+    // GCLK5: 48MHz, source: DFLL48M, usage: USB
+    // DFLL48M: Reference sources:
+    //          - in closed loop mode: eiter XOSC32K or OSCULP32K or USB clock
+    //          - in open loop mode: None
     // DPLL0: 48 - 200 MHz
 
     // Steps to set up clocks: