stm32/qspi.c: Allow qspi_write_cmd_data to write cmd with 1 data byte. #11931
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qspi_write_cmd_data to write a cmd with 1 byte of data
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When initialising flash, write the second byte of SR as a separate command in addition to writing both bytes. Some flash chips require seperate write commands for the first and second bytes of the SR. In this case, we are only setting the Quad Enable bit on the second byte of the SR. If the flash chip only supports a multi-byte SR write, then the original SR write will succeed. If the flash chip only supports a single-byte SR write, only the second byte needs to be written as the first byte is unchanged for quad enable. If the flash chip supports both, then they will both be executed but still set the quad enable bit. If the chip doesn't support one of the commands, it should silently ignore the command and the other one should succeed. Depends on micropython#11931 for this to work on stm32 Signed-off-by: Victor Rajewski <victor@allumeenergy.com.au>
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The existing spiflash driver writes both bytes of SR as a single command. Some flash chips don't support multi-byte writes such as this, and have a seperate command to write SR byte 1 and SR byte 2 (referred to in the code as CR). This used in the spiflash initialisation to enable quad mode. The quad enable bit is in the second SR byte. This change still issues the multi-byte command, then issues a single byte command for just the second SR byte. For chips that only support one of the commands, the unsupported command should be ignored silently. For chips that support both types of command, the SR will be written twice. This depends on micropython#11931 for the stm32 port to allow single-byte spi commands. Signed-off-by: Victor Rajewski <victor@allumeenergy.com.au>
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The existing spiflash driver writes both bytes of SR as a single command. Some flash chips don't support multi-byte writes such as this, and have a seperate command to write SR byte 1 and SR byte 2 (referred to in the code as CR). This used in the spiflash initialisation to enable quad mode. The quad enable bit is in the second SR byte. This change still issues the multi-byte command, then issues a single byte command for just the second SR byte. For chips that only support one of the commands, the unsupported command should be ignored silently. For chips that support both types of command, the SR will be written twice. This depends on micropython#11931 for the stm32 port to allow single-byte spi commands. Signed-off-by: Victor Rajewski <victor@allumeenergy.com.au>
The existing qspi for stm32 implementation can only send a spi command with exactly 0 or 2 data bytes. Certain spiflash chips (e.g. AT25SF321B) have commands that only take a single data byte, and will ignore the command if more than that is sent. This commit allows sending a command with a single data byte. Signed-off-by: Victor Rajewski <victor@allumeenergy.com.au>
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The existing qspi for stm32 implementation can only send a spi command with exactly 0 or 2 data bytes. Certain spiflash chips (e.g. AT25SF321B) have commands that only take a single data byte, and will ignore the command if more than that is sent. This allows sending a command with a single data byte. Would be nicer to have a general function to send
nbytes, but there probably aren't many commands that require this.