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Reorg logical flow in train #37
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674526d
Add new config about knowledge distillation for query binary classifier
59d6318
remove inferenced result in knowledge distillation for query binary c…
chengfx b4c110e
Add AUC.py in tools folder
chengfx 891f43a
Add test_data_path into conf_kdqbc_bilstmattn_cnn.json
chengfx 8b1d100
Modify AUC.py
chengfx 333bd98
Rename AUC.py into calculate_AUC.py
chengfx b6523a7
Merge branch 'master' into dev/fecheng
chengfx 74976c2
Modify test&calculate AUC commands for Knowledge Distillation for Que…
chengfx 936d9fe
Merge branch 'master' into dev/fecheng
chengfx 8c6e61b
Add cpu_thread_num parameter in conf.training_params
chengfx 69c0bca
Rename cpu_thread_num into cpu_num_workers
chengfx fb11aba
update comments in ModelConf.py
chengfx bbfcde2
Add cup_num_workers in model_zoo/advanced/conf.json
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Add the description of cpu_num_workers in Tutorial.md
chengfx 4c9380c
fix conflict
chengfx 2ae9d4a
Merge branch 'master' into dev/fecheng
chengfx cff4cd3
Update inference speed of compressed model
chengfx cf534ce
Add ProcessorsScheduler Class
chengfx 37d09d5
Merge branch 'master' into dev/fecheng
chengfx 17b8447
Add license in ProcessorScheduler.py
chengfx e087427
use lazy loading instead of one-off loading
chengfx 1fb0440
merge master
chengfx 05ddcf8
Remove Debug Info in problem.py
chengfx af6ea60
use open instead of codecs.open
chengfx 535649e
Merge branch 'master' into dev/fecheng
chengfx fb4e47b
update the inference of build dictionary for classification
chengfx a3a0c25
add md5 function in common_utils.py
chengfx 889aa91
add merge_encode_* function
chengfx bab7f54
update typo
chengfx 576b88d
update typo
chengfx 91440a5
reorg the logical flow in train.py
chengfx 5a747e6
Merge branch 'add_encoding_cache' into dev/fecheng
chengfx 229622b
merge master
chengfx 49a32fe
remove dummy comments in problem.py
chengfx 627a80f
enumerate problem types in problem.py
chengfx fbf780d
remove data_encoding.py
chengfx c735b45
Modify comment and remove debug code
chengfx d6566d4
merge master
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Original file line number | Diff line number | Diff line change |
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@@ -3,4 +3,5 @@ | |
*.pyc | ||
*.cache* | ||
dataset/GloVe/ | ||
dataset/20_newsgroups/ | ||
models/ |
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readability is not good, I think. Strongly suggest enumerate every task.
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Hi, @woailaosang Readability is just special for train logical flow here. I made less works on other modules. Yeah, enumerate every task is a good idea . But I think we need to optimize the code to reduce the repeated codes and logic. Otherwise you have to modify every place if you want to make some changes