mmreg fix pollable interrupt status
#17
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I don't see intr_stat being removed in the code change. We probably should leave intr_stat in the readable space since it provides a way for software to poll the completion status without enabling interrupt. Also, please leave the dbg fifo in for now. The feature was required for FPGA debugging (by Wes I think). Basically we need a fast printf (compared to UART) to dump information when debugging firmware. Inserting UART printfs might change the software timing too much and make it harder to reproduce issues. |
Both tbre_go and tbre_intr_stat are only asserted for one cycle so it does not make sense to have these be exposed as a register that can be read from the bus.
Previously the interrupt status could be polled when interrupts were disabled but there was no way to clear the interrupt. This commits allows reading out the interrupt status again and added clearing logic.
This makes it more clear from code inspection that register address 2 exists because it is in the case statement.
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mmreg remove debugmmreg fix pollable interrupt status
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Thanks @kliuMsft ! I've put the debug logic back in. I've put the interrupt status back into the readable space and also added it to the writable space so that it can be cleared in case interrupts are not enabled. Let me know what you think. |
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Looks good, thanks Marno. Merging. |
This essentially removes the debug signals and wires from the
mmregmodule. It doesn't make much sense to expose these to software and with hardware simulation you can derive these signals from existing ones.It also removes
tbre_goandtbre_intr_statfrom the read register interface. These signals are only set for one cycle and it doesn't make sense to expose that over a bus interface.