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5 contributions in the last year

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Contribution activity

May 2019

Created an issue in riscv/riscv-isa-sim that received 3 comments

PATCH: Don't need to set MSTATUS_UXL/SXL for RV32.

For RV32, mstatus will be set to 0x5 0000 0000 in processor_t::reset(). It's not reasonable. Refer to 3.1.8, Privileged Architecture Version 1.10: …

3 comments

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