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Merge pull request f4pga#92 from SymbiFlow/tilegrid-ng
Tilegrid changes for BRAM and DSP tiles
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/specimen_*/ | ||
*.yaml | ||
/run.ok |
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/specimen_*/ | ||
/tilegrid.json | ||
/run.ok |
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/specimen_[0-9][0-9][0-9]/ | ||
/seg_clbl[lm].segbits | ||
/run.ok |
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/specimen_* | ||
/__pycache__/ | ||
/*.segbits | ||
/run.ok |
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/*.segbits | ||
/vivado.log | ||
/vivado.jou | ||
/run.ok |
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/specimen_*/ | ||
/*.segbits | ||
/run.ok |
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/vivado* | ||
/specimen_* | ||
/*.segbits | ||
/run.ok |
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/*.segbits | ||
/vivado.log | ||
/vivado.jou | ||
/run.ok |
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/specimen_[0-9][0-9][0-9]/ | ||
/seg_int_[lr].segbits | ||
/mask_clbl[lm]_[lr].segbits | ||
/run.ok |
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/specimen_[0-9][0-9][0-9]/ | ||
/todo.txt | ||
/vivado* | ||
/run.ok |
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/specimen_[0-9][0-9][0-9]/ | ||
/todo.txt | ||
/vivado* | ||
/run.ok |
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@@ -11,3 +11,4 @@ | |
/specimen_[0-9][0-9][0-9]/ | ||
/todo.txt | ||
/vivado* | ||
/run.ok |
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@@ -11,3 +11,4 @@ | |
/specimen_[0-9][0-9][0-9]/ | ||
/todo.txt | ||
/vivado* | ||
/run.ok |
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@@ -11,3 +11,4 @@ | |
/specimen_[0-9][0-9][0-9]/ | ||
/todo.txt | ||
/vivado* | ||
/run.ok |
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@@ -11,3 +11,4 @@ | |
/specimen_[0-9][0-9][0-9]/ | ||
/todo.txt | ||
/vivado* | ||
/run.ok |
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/specimen_*/ | ||
/tileconn.json | ||
/run.ok |
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/specimen_*/ | ||
/ppips_clbl[ml]_[lr].txt | ||
/ppips_int_[lr].txt | ||
/run.ok |
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/specimen_[0-9][0-9][0-9]/ | ||
/seg_dsp_[lr].segbits | ||
/run.ok |
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N := 1 | ||
SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N))) | ||
SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS)) | ||
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database: $(SPECIMENS_OK) | ||
${XRAY_SEGMATCH} -o seg_dsp_l.segbits $(addsuffix /segdata_dsp_l_*.txt,$(SPECIMENS)) | ||
${XRAY_SEGMATCH} -o seg_dsp_r.segbits $(addsuffix /segdata_dsp_r_*.txt,$(SPECIMENS)) | ||
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pushdb: | ||
${XRAY_MERGEDB} dsp_l seg_dsp_l.segbits | ||
${XRAY_MERGEDB} dsp_r seg_dsp_r.segbits | ||
${XRAY_DBFIXUP} | ||
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$(SPECIMENS_OK): | ||
bash generate.sh $(subst /OK,,$@) | ||
touch $@ | ||
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run: | ||
$(MAKE) clean | ||
$(MAKE) database | ||
$(MAKE) pushdb | ||
touch run.ok | ||
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clean: | ||
rm -rf specimen_[0-9][0-9][0-9]/ seg_dsp_l.segbits seg_dsp_r.segbits run.ok | ||
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.PHONY: database pushdb run clean | ||
|
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#!/usr/bin/env python3 | ||
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import sys, os, re | ||
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sys.path.append("../../../utils/") | ||
from segmaker import segmaker | ||
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segmk = segmaker("design_%s.bits" % sys.argv[1]) | ||
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pipdata = dict() | ||
ignpip = set() | ||
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print("Loading tags from design.txt.") | ||
with open("design_%s.txt" % sys.argv[1], "r") as f: | ||
for line in f: | ||
tile, loc, mask, pattern = line.split() | ||
dsp = "DSP_0" if loc[-1] in "02468" else "DSP_1" | ||
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mask = int(mask.replace("48'h", ""), 16) | ||
pattern = int(pattern.replace("48'h", ""), 16) | ||
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for i in range(48): | ||
segmk.addtag(tile, "%s.MASK[%d]" % (dsp, i), (mask >> i) & 1) | ||
segmk.addtag(tile, "%s.PATTERN[%d]" % (dsp, i), (pattern >> i) & 1) | ||
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segmk.compile() | ||
segmk.write(suffix=sys.argv[1]) |
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#!/bin/bash | ||
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source ${XRAY_GENHEADER} | ||
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vivado -mode batch -source ../generate.tcl | ||
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for i in {10..29}; do | ||
${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design_${i}.bits -z -y design_${i}.bit | ||
python3 ../generate.py $i | ||
done | ||
|
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create_project -force -part $::env(XRAY_PART) design design | ||
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read_verilog ../top.v | ||
synth_design -top top | ||
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] | ||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o] | ||
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create_pblock roi | ||
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" | ||
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set_property CFGBVS VCCO [current_design] | ||
set_property CONFIG_VOLTAGE 3.3 [current_design] | ||
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] | ||
set_param tcl.collectionResultDisplayLimit 0 | ||
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place_design | ||
route_design | ||
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write_checkpoint -force design.dcp | ||
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source ../../../utils/utils.tcl | ||
set cells [list] | ||
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set gnd_net [create_net gnd_net] | ||
set gnd_cell [create_cell -reference GND gnd_cell] | ||
connect_net -net $gnd_net -objects [get_pins $gnd_cell/G] | ||
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foreach site [get_sites -of_objects [filter [roi_tiles] -filter {TYPE == "DSP_L" || TYPE == "DSP_R"}] -filter {SITE_TYPE =~ DSP*}] { | ||
set cell [create_cell -reference DSP48E1 ${site}_cell] | ||
lappend cells $cell | ||
set_property LOC $site $cell | ||
foreach pin [get_pins -of_objects $cell -filter {DIRECTION == "IN"}] { | ||
connect_net -net $gnd_net -objects $pin | ||
} | ||
} | ||
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route_design | ||
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proc write_txtdata {filename} { | ||
upvar 1 cells cells | ||
puts "Writing $filename." | ||
set fp [open $filename w] | ||
foreach cell $cells { | ||
set loc [get_property LOC $cell] | ||
set mask [get_property MASK $cell] | ||
set pattern [get_property PATTERN $cell] | ||
set tile [get_tiles -of_objects [get_sites -filter "NAME == $loc"]] | ||
puts $fp "$tile $loc $mask $pattern" | ||
} | ||
close $fp | ||
} | ||
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proc randhex {len} { | ||
set s "" | ||
for {set i 0} {$i < $len} {incr i} { | ||
set s "$s[format %x [expr {int(rand()*16)}]]" | ||
} | ||
return $s | ||
} | ||
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for {set i 10} {$i < 30} {incr i} { | ||
foreach cell $cells { | ||
set_property MASK "48'h[randhex 12]" $cell | ||
set_property PATTERN "48'h[randhex 12]" $cell | ||
} | ||
write_checkpoint -force design_${i}.dcp | ||
write_bitstream -force design_${i}.bit | ||
write_txtdata design_${i}.txt | ||
} | ||
|
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module top (input i, output o); | ||
assign o = i; | ||
endmodule |
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