Merge pull request f4pga#1735 from HackerFoo/flags_reduce_runtime

Adjust VPR flags to reduce runtime

requirements.txt

@@ -1,6 +1,6 @@
 cairosvg
 gitpython
-hilbertcurve
+hilbertcurve==1.0.5
 intervaltree
 matplotlib
 numpy

xc/common/cmake/arch_define.cmake

@@ -61,11 +61,24 @@ function(ADD_XC_ARCH_DEFINE)
   set(YOSYS_CONV_SCRIPT ${ADD_XC_ARCH_DEFINE_YOSYS_CONV_SCRIPT})
   set(YOSYS_UTILS_SCRIPT ${ADD_XC_ARCH_DEFINE_YOSYS_UTILS_SCRIPT})
   set(YOSYS_TECHMAP ${symbiflow-arch-defs_SOURCE_DIR}/xc/${FAMILY}/techmap)
+
+  # Notes on optimized flag settings:
+  # These flags have been optimized for the ibex and baselitex designs.
+  # - place_delay_model: delta is ~5% faster than delta_override (default: delta)
+  # - acc_fac: Lowering this to 0.7 slightly improves runtime 1-4% (default: 1)
+  # - astar_fac: Increasing this to 1.8 reduces runtime 2-15% (default: 1.2)
+  # - initial_pres_fac: Setting this to 2.828 reduces runtime 10-20% from the default,
+  #   and about 3% faster than the previous value of 4 (default: 0.5)
+  # - pres_fac_mult: A lower value of 1.2 performs better given the other parameters (default: 1.3)
+  # Based on analysis performed on hydra.vtr.tools for the ibex, baselitex, and bram-n3 designs.
+  # These changes did not have a measurable effect on QoR for these designs.
+  # More details can be found in the report: https://colab.research.google.com/drive/1X91RGZnvlC7dBjJJUbS7JfqCbPCzJ3Xb
+  # Also checked in at: utils/ipynb/Parameter_Sweep_using_fpga_tool_perf.ipynb
   set(VPR_ARCH_ARGS "\
       --router_heap bucket \
       --clock_modeling route \
       --place_delta_delay_matrix_calculation_method dijkstra \
-      --place_delay_model delta_override \
+      --place_delay_model delta \
       --router_lookahead extended_map \
       --check_route quick \
       --strict_checks off \
@@ -75,7 +88,10 @@ function(ADD_XC_ARCH_DEFINE)
       --incremental_reroute_delay_ripup off \
       --base_cost_type delay_normalized_length_bounded \
       --bb_factor 10 \
-      --initial_pres_fac 4.0 \
+      --acc_fac 0.7 \
+      --astar_fac 1.8 \
+      --initial_pres_fac 2.828 \
+      --pres_fac_mult 1.2 \
       --check_rr_graph off \
       --suppress_warnings \${OUT_NOISY_WARNINGS},sum_pin_class:check_unbuffered_edges:load_rr_indexed_data_T_values:check_rr_node:trans_per_R:check_route:set_rr_graph_tool_comment:calculate_average_switch"
       )

xc/xc7/tests/install_test/Makefile

@@ -9,7 +9,7 @@ VERILOG:=${current_dir}/counter_${BOARD}.v
 PCF=${current_dir}/${BOARD}.pcf
 XDC=${current_dir}/counter_${BOARD}.xdc
 BUILDDIR:=build
-ADDITIONAL_VPR_OPTIONS="--seed 1024 --astar_fac 1.3"
+ADDITIONAL_VPR_OPTIONS="--seed 1024"
 
 all: ${BUILDDIR}/${TOP}.bit