Merge pull request f4pga#1792 from antmicro/fd-techmap

yosys: add retargeting step for FD primitives
mithro · Nov 20, 2020 · d5f8ce8 · d5f8ce8
2 parents ac53394 + 1b4c16a
commit d5f8ce8
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diff --git a/xc/xc7/techmap/retarget.v b/xc/xc7/techmap/retarget.v
@@ -0,0 +1,7 @@
+module FD (output reg Q, input C, D);
+
+parameter [0:0] INIT = 1'b0;
+
+FDRE #(.INIT(INIT)) __TECHMAP_REPLACE__ (.Q(Q), .C(C), .D(D), .CE(1'b1), .R(1'b0));
+
+endmodule
diff --git a/xc/xc7/yosys/synth.tcl b/xc/xc7/yosys/synth.tcl
@@ -25,6 +25,9 @@ if { $::env(USE_ROI) == "TRUE" } {
     # Overwrite some models (e.g. IBUF with more parameters)
     read_verilog -lib $::env(TECHMAP_PATH)/iobs.v
 
+    # Re-targetting FD to FDREs
+    techmap -map  $::env(TECHMAP_PATH)/retarget.v
+
     hierarchy -check -auto-top
 
     # Start flow after library reading