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Added (untested) auto mode for vbd.

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RedGuyyyy committed Sep 8, 2018
1 parent d408602 commit 5dfad7b12e3342feb73804a85800103bd736cb6e
Showing with 31 additions and 23 deletions.
  1. +26 −18 verilog/sd2snes_sa1/sa1.v
  2. +5 −5 verilog/sd2snes_sa1/sd2snes.xise
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@@ -122,7 +122,7 @@ module sa1(
// [x] mac support for multiply
// [_] full mdr support
// [x] variable length data/fixed
// [_] variable length data/auto
// [x] variable length data/auto
//-------------------------------------------------------------------
// DEFINES
@@ -2117,8 +2117,9 @@ assign dma_mmc_cc1_mask = dma_cc1_imask_r;
// auto - write address, write control, [not currently supported]
parameter
ST_VBD_IDLE = 8'b00000001,
ST_VBD_READ_END = 8'b00000010,
ST_VBD_SHIFT = 8'b00000100,
ST_VBD_READ = 8'b00000010,
ST_VBD_READ_END = 8'b00000100,
ST_VBD_SHIFT = 8'b00001000,
ST_VBD_ALL = 8'b11111111;
reg [7:0] VBD_STATE; initial VBD_STATE = ST_VBD_IDLE;
@@ -2127,6 +2128,7 @@ reg [23:0] VBA_r; initial VBA_r = 0;
reg [4:0] vbd_temp;
reg [3:0] vbd_vbit_r; initial vbd_vbit_r = 0;
reg vbd_trigger_r; initial vbd_trigger_r = 0;
reg vbd_update_r; initial vbd_update_r = 0;
reg [31:0] vbd_data_r;
reg vbd_active_r; initial vbd_active_r = 0;
@@ -2139,38 +2141,44 @@ always @(posedge CLK) begin
VDP_r <= 0;
vbd_vbit_r <= 0;
vbd_trigger_r <= 0;
vbd_update_r <= 0;
vbd_active_r <= 0;
VBD_STATE <= ST_VBD_IDLE;
end
else begin
// watch for triggers
vbd_trigger_r <= VBD_r[`VBD_HL] ? (1'b0 && (snes_readbuf_val_r | sa1_readbuf_val_r) && snes_readbuf_mmio_addr_r[8:0] == ADDR_VDP+1) : (snes_writebuf_val_r && (snes_writebuf_addr_r[8:0] == ADDR_VDA+2 || snes_writebuf_addr_r[8:0] == ADDR_VBD));
// HL=0 trigger on VBA+2 and every VBD write. HL=1 trigger on VDP+1 data read and every VBD write.
vbd_trigger_r <= (VBD_r[`VBD_HL] && sa1_mmio_read_r[1] && snes_readbuf_mmio_addr_r[8:0] == ADDR_VDP+1) || (snes_writebuf_val_r && ((~VBD_r[`VBD_HL] && snes_writebuf_addr_r[8:0] == ADDR_VDA+2) || snes_writebuf_addr_r[8:0] == ADDR_VBD));
// HL=0 update on VBD write. needs to sync'ed with trigger to get new register value. this is done by adding the extra READ stage. HL=1 update on data written to VDP
vbd_update_r <= (snes_writebuf_val_r && snes_writebuf_addr_r[8:0] == ADDR_VBD && ~snes_writebuf_data_r[`VBD_HL]) || (VBD_STATE[clog2(ST_VBD_SHIFT)] && VBD_r[`VBD_HL]);
case (VBD_STATE)
ST_VBD_IDLE: begin
if (snes_writebuf_val_r) begin
if (vbd_update_r) begin
vbd_temp = {1'b0,vbd_vbit_r} + {~|VBD_r[`VBD_VB],VBD_r[`VBD_VB]};
vbd_vbit_r <= vbd_temp[3:0];
VDA_r <= VDA_r[23:0] + {vbd_temp[4],1'b0};
end
else if (snes_writebuf_val_r) begin
if (snes_writebuf_addr_r[8:0] == ADDR_VDA+0) VDA_r[7 : 0] <= snes_writebuf_data_r;
else if (snes_writebuf_addr_r[8:0] == ADDR_VDA+1) VDA_r[15: 8] <= snes_writebuf_data_r;
else if (snes_writebuf_addr_r[8:0] == ADDR_VDA+2) begin VDA_r[23:16] <= snes_writebuf_data_r; vbd_vbit_r <= 0; end
else if (snes_writebuf_addr_r[8:0] == ADDR_VBD ) begin
if (~snes_writebuf_data_r[`VBD_HL]) begin
vbd_temp = {1'b0,vbd_vbit_r} + {~|snes_writebuf_data_r[`VBD_VB],snes_writebuf_data_r[`VBD_VB]};
vbd_vbit_r <= vbd_temp[3:0];
VDA_r <= VDA_r[23:0] + {vbd_temp[4],1'b0};
end
end
end
else if (vbd_trigger_r) begin
vbd_mmc_rd_r <= 1;
vbd_mmc_addr_r <= VDA_r;
if (vbd_trigger_r) begin
vbd_active_r <= 1;
VBD_STATE <= ST_VBD_READ_END;
VBD_STATE <= ST_VBD_READ;
end
end
ST_VBD_READ: begin
vbd_mmc_rd_r <= 1;
vbd_mmc_addr_r <= VDA_r;
VBD_STATE <= ST_VBD_READ_END;
end
ST_VBD_READ_END: begin
if (MMC_STATE[clog2(ST_MMC_VBD_END)]) begin
vbd_mmc_rd_r <= 0;
@@ -170,7 +170,7 @@
<property xil_pn:name="Case Implementation Style" xil_pn:value="Full-Parallel" xil_pn:valueState="non-default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="true" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -217,7 +217,7 @@
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort" xil_pn:value="Normal" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
@@ -272,7 +272,7 @@
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Timing Performance" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="SmartXplorer - maptiming1;C:/Users/O/dev/sd2snes_sa1b/verilog/sd2snes_sa1/maptiming1.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="SmartXplorer - mapphyssynthesis;C:/Users/O/dev/sd2snes_sa1b/verilog/sd2snes_sa1/mapphyssynthesis.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
@@ -358,7 +358,7 @@
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="On" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
@@ -451,7 +451,7 @@
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Users/O/dev/sd2snes_sa1b/verilog/sd2snes_sa1/maptiming1.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Users/O/dev/sd2snes_sa1b/verilog/sd2snes_sa1/mapphyssynthesis.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>

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