Skip to content
Permalink
Browse files

FPGA: free some block RAM when using ChipScope

  • Loading branch information...
mrehkopf committed Jul 5, 2019
1 parent df72413 commit 899c8139fc796f665ff36410b6e2fd426bb24411
Showing with 14 additions and 0 deletions.
  1. +4 −0 verilog/sd2snes_cx4/dac.v
  2. +4 −0 verilog/sd2snes_cx4/msu.v
  3. +6 −0 verilog/sd2snes_gsu/dac.v
@@ -18,6 +18,8 @@
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"

module dac(
input clkin,
input sysclk,
@@ -56,6 +58,7 @@ always @(posedge clkin) begin
end

`ifdef MK2
`ifndef DEBUG
dac_buf snes_dac_buf (
.clka(clkin),
.wea(~we), // Bus [0 : 0]
@@ -65,6 +68,7 @@ dac_buf snes_dac_buf (
.addrb(dac_address), // Bus [8 : 0]
.doutb(dac_data)); // Bus [31 : 0]
`endif
`endif

`ifdef MK3
dac_buf snes_dac_buf (
@@ -18,6 +18,8 @@
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"

module msu(
input clkin,
input enable,
@@ -112,6 +114,7 @@ assign status_out = {msu_address_r[13], // 7
initial msu_address_r = 14'h1234;

`ifdef MK2
`ifndef DEBUG
msu_databuf snes_msu_databuf (
.clka(clkin),
.wea(~pgm_we), // Bus [0 : 0]
@@ -122,6 +125,7 @@ msu_databuf snes_msu_databuf (
.doutb(msu_data)
); // Bus [7 : 0]
`endif
`endif
`ifdef MK3
msu_databuf snes_msu_databuf (
.clock(clkin),
@@ -18,6 +18,8 @@
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"

module dac(
input clkin,
input sysclk,
@@ -63,6 +65,7 @@ always @(posedge clkin) begin
sysclk_sreg <= {sysclk_sreg[1:0], sysclk};
end
`ifdef MK2
`ifndef DEBUG
dac_buf snes_dac_buf (
.clka(clkin),
.wea(~we), // Bus [0 : 0]
@@ -72,6 +75,8 @@ dac_buf snes_dac_buf (
.addrb(dac_address), // Bus [8 : 0]
.doutb(dac_data)); // Bus [31 : 0]
`endif
`endif

`ifdef MK3
dac_buf snes_dac_buf (
.clock(clkin),
@@ -81,6 +86,7 @@ dac_buf snes_dac_buf (
.rdaddress(dac_address), // Bus [8 : 0]
.q(dac_data)); // Bus [31 : 0]
`endif

reg [10:0] cnt;
reg [15:0] smpcnt;
reg [1:0] samples;

0 comments on commit 899c813

Please sign in to comment.
You can’t perform that action at this time.