Thanks to Eng. Ahmed Ramadan for his contribution in collecting these material.
1- "PLL System-Level":
Understand the general operation of PLLs + how to derive the open & closed loop equations.
a) Start with CH 16 of Prof. Razavi's reference "Design of Analog CMOS Integrated Circuits" 3rd ed.
b) Follow the equations in Prof. Sang-Soo Lee's EE230 lecture notes.
=> [Project] Generate the open-loop & the closed-loop Bode Plots using Matlab & VerilogA.
2- "PLL Circuit Blocks":
Understand how to build each building block on the transistor level.
a) Prof. Sam Palermo's ECEN620 lecture notes explain the specifics of each block along with showing the common topologies.
b) Eng. Dennis Fischette's Tutorial presents practical tips for building PLL blocks based on what's done in industry.
=> [Project] Build each individual block on Cadence Virtuoso.
3- "Jitter & Phase Noise Understanding":
Understand the relationship between phase noise & jitter + understand how each block contributes to the total phase noise.
a) Check the technical notes about PLL jitter & phase noise below.
=> [Project] Connect all the circuit blocks together, & optimize based on the jitter & the phase noise requirements.
|
Course |
Instructor |
Affiliation |
Material |
PLL Lectures |
|
|
|
|
|
|
| 1 |
EE 230 : "RFIC II" |
Dr. Sang-Soo Lee |
SJSU |
(Material) |
Lecs: 16 - 21 |
| 2 |
ECEN 620: "Network Theory: Broadband Circuit Design" |
Dr. Sam Palermo |
Texas A&M Univ |
(Site) (Material) |
Lecs: 1 - 11 |
| 3 |
ECE 504: "PLL & High-Speed Link design" |
Dr. Vishal Saxena |
Univ of Idaho |
(Material) |
Lecs: ALL |
| 4 |
"High-Speed Serial Interface Circuits & Systems" |
Dr. Woo Choi |
Yonsei Univ |
(Site) (Material) |
Lecs: 1 - 5 |
|
|
|
|
| 1 |
"Design of Analog CMOS Integrated Circuits" - CH 16 |
by Razavi |
(Ref) |
| 2 |
"Design of CMOS PLLs" |
by Razavi |
(Ref) |
|
|
|
|
| 1 |
"Practical Tips for PLL Design" |
Dennis Fischette |
(Site) (Docs) |
| 2 |
"PLL Fundamentals" |
Dean Banerjee - TI |
(Slides) (Book) |
| 3 |
Jitter & Phase Noise |
|
|
|
(A) "Converting Oscillator Phase Noise to Time Jitter" |
Walt Kester - AnalogDevices |
(Docs) |
|
(B) "Phase Locked Loop Noise Transfer Functions" |
Peter Delos - LockheedMartin |
(Docs) |
|
(C) "Timing Jitter - Tutorial & Measurement Guide" |
Silicon Labs Timing |
(Docs) |
|
(D) ISSCC2012: "Jitter basics and advanced concepts" |
Nicola Da Dalt - Infineon |
(Docs) |
|
(E) ESSCIRC2019: "Fundamental Concepts in Jitter and Phase Noise" |
Ali Sheikholeslami - Univ of Toronto |
(Docs) |
|
|
|
|
| 1 |
"1.9-GHz PLL design" |
(Repo) |
|
| 2 |
PLL Masters Thesis by Rishi Ratan |
(Report) (Site) |
|
Google Drive: (Link)