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generating vivado tcl file from makefile
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Oliver Dippel
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Nov 6, 2023
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,15 +1,54 @@ | ||
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| all: build/rio.bit | ||
| PROJECT = rio | ||
| TOP = rio | ||
| PART = xc7a35ticsg324-1l | ||
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| build/rio.bit: rio.tcl pins.xdc blink.v rio.v | ||
| vivado -mode batch -source rio.tcl | ||
| all: build/$(PROJECT).bit | ||
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| $(PROJECT).tcl: pins.xdc blink.v $(PROJECT).v | ||
| @echo "set outputDir ./build" > $(PROJECT).tcl | ||
| @echo "file mkdir \$$outputDir" >> $(PROJECT).tcl | ||
| @echo "" >> $(PROJECT).tcl | ||
| @for VAR in $?; do echo $$VAR | grep -s -q "\.v$$" && echo "read_verilog $$VAR" >> $(PROJECT).tcl; done | ||
| @echo "read_xdc pins.xdc" >> $(PROJECT).tcl | ||
| @echo "" >> $(PROJECT).tcl | ||
| @echo "synth_design -top $(TOP) -part $(PART)" >> $(PROJECT).tcl | ||
| @echo "write_checkpoint -force \$$outputDir/post_synth.dcp" >> $(PROJECT).tcl | ||
| @echo "report_timing_summary -file \$$outputDir/post_synth_timing_summary.rpt" >> $(PROJECT).tcl | ||
| @echo "report_utilization -file \$$outputDir/post_synth_util.rpt" >> $(PROJECT).tcl | ||
| @echo "" >> $(PROJECT).tcl | ||
| @echo "opt_design" >> $(PROJECT).tcl | ||
| @echo "place_design" >> $(PROJECT).tcl | ||
| @echo "report_clock_utilization -file \$$outputDir/clock_util.rpt" >> $(PROJECT).tcl | ||
| @echo "" >> $(PROJECT).tcl | ||
| @echo "write_checkpoint -force \$$outputDir/post_place.dcp" >> $(PROJECT).tcl | ||
| @echo "report_utilization -file \$$outputDir/post_place_util.rpt" >> $(PROJECT).tcl | ||
| @echo "report_timing_summary -file \$$outputDir/post_place_timing_summary.rpt" >> $(PROJECT).tcl | ||
| @echo "" >> $(PROJECT).tcl | ||
| @echo "route_design" >> $(PROJECT).tcl | ||
| @echo "write_checkpoint -force \$$outputDir/post_route.dcp" >> $(PROJECT).tcl | ||
| @echo "report_route_status -file \$$outputDir/post_route_status.rpt" >> $(PROJECT).tcl | ||
| @echo "report_timing_summary -file \$$outputDir/post_route_timing_summary.rpt" >> $(PROJECT).tcl | ||
| @echo "report_power -file \$$outputDir/post_route_power.rpt" >> $(PROJECT).tcl | ||
| @echo "report_drc -file \$$outputDir/post_imp_drc.rpt" >> $(PROJECT).tcl | ||
| @echo "" >> $(PROJECT).tcl | ||
| @echo "write_verilog -force \$$outputDir/impl_netlist.v -mode timesim -sdf_anno true" >> $(PROJECT).tcl | ||
| @echo "" >> $(PROJECT).tcl | ||
| @echo "write_bitstream -force \$$outputDir/$(PROJECT).bit" >> $(PROJECT).tcl | ||
| @echo "" >> $(PROJECT).tcl | ||
| @echo "exit" >> $(PROJECT).tcl | ||
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| build/$(PROJECT).bit: $(PROJECT).tcl | ||
| vivado -mode batch -source $(PROJECT).tcl | ||
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| clean: | ||
| rm -rf build | ||
| rm -rf build $(PROJECT).tcl vivado.jou vivado.log .Xil | ||
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| xc3sprog: build/rio.bit | ||
| xc3sprog -c nexys4 build/rio.bit | ||
| xc3sprog: build/$(PROJECT).bit | ||
| xc3sprog -c nexys4 build/$(PROJECT).bit | ||
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| load: build/rio.bit | ||
| openFPGALoader -b arty -f build/rio.bit | ||
| load: build/$(PROJECT).bit | ||
| openFPGALoader -b arty -f build/$(PROJECT).bit | ||
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