Merge pull request #147 from jandecaluwe/mep-114

MEP 114

cosimulation/test/bin2gray.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 def bin2gray(B, G, width):

cosimulation/test/dff.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 ACTIVE_LOW, INACTIVE_HIGH = 0, 1

cosimulation/test/dff_clkout.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 from dff import dff

cosimulation/test/inc.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 ACTIVE_LOW, INACTIVE_HIGH = 0, 1

example/arith_lib/Dec.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 from arith_utils import BEHAVIOR
 from PrefixAnd import PrefixAnd

example/arith_lib/LeadZeroDet.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 from arith_utils import BEHAVIOR
 from PrefixAnd import PrefixAnd

example/arith_lib/PrefixAnd.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 from arith_utils import log2ceil

example/arith_lib/test_Dec.py

@@ -1,6 +1,7 @@
 import unittest
 from unittest import TestCase
 
+import myhdl
 from myhdl import *
 
 from arith_utils import BEHAVIOR, STRUCTURE

example/arith_lib/test_LeadZeroDet.py

@@ -1,6 +1,7 @@
 import unittest
 from unittest import TestCase
 
+import myhdl
 from myhdl import *
 
 from arith_utils import BEHAVIOR, STRUCTURE

example/cookbook/bitonic/bitonic.py

@@ -1,87 +1,94 @@
 import subprocess
 
+import myhdl
 from myhdl import *
 from myhdl.conversion import analyze
 
 DESCENDING, ASCENDING = False, True
 
-def compare(a1, a2, z1, z2, dir):
-
+@block
+def comp(a1, a2, z1, z2, dir):
+
     @always_comb
     def logic():
         z1.next = a1
         z2.next = a2
         if dir == (a1 > a2):
             z1.next = a2
             z2.next = a1
-            
+
     return logic
 
 
+@block
 def feedthru(a, z):
-    
+
     @always_comb
     def logic():
         z.next = a
-        
+
     return logic
 
 
+@block
 def bitonicMerge(a, z, dir):
-    
+
     n = len(a)
     k = n//2
     w = len(a[0])
-    
+
     if n > 1:
         t = [Signal(intbv(0)[w:]) for i in range(n)]
-        comp = [compare(a[i], a[i+k], t[i], t[i+k], dir) for i in range(k)]
-        loMerge = bitonicMerge(t[:k], z[:k], dir)
-        hiMerge = bitonicMerge(t[k:], z[k:], dir)
-        return comp, loMerge, hiMerge
+        comps = [comp(a[i], a[i+k], t[i], t[i+k], dir) for i in range(k)]
+        lomerge = bitonicMerge(t[:k], z[:k], dir)
+        himerge = bitonicMerge(t[k:], z[k:], dir)
+        lomerge.name = "lomerge"
+        himerge.name = "hiMerge"
+        return comps, lomerge, himerge
     else:
-        feed = feedthru(a[0], z[0])
-        return feed
+        return feedthru(a[0], z[0])
 
 
+@block
 def bitonicSort(a, z, dir):
-    
+
     n = len(a)
     k = n//2
     w = len(a[0])
-    
+
     if n > 1:
         t = [Signal(intbv(0)[w:]) for i in range(n)]
-        loSort = bitonicSort(a[:k], t[:k], ASCENDING)
-        hiSort = bitonicSort(a[k:], t[k:], DESCENDING)
+        losort = bitonicSort(a[:k], t[:k], ASCENDING)
+        hisort = bitonicSort(a[k:], t[k:], DESCENDING)
         merge = bitonicMerge(t, z, dir)
-        return loSort, hiSort, merge
+        losort.name = "losort"
+        hisort.name = "hisort"
+        merge.name = "merge"
+        return losort, hisort, merge
     else:
-        feed = feedthru(a[0], z[0])
-        return feed
-
+        return feedthru(a[0], z[0])
 
+@block
 def Array8Sorter(a0, a1, a2, a3, a4, a5, a6, a7,
                  z0, z1, z2, z3, z4, z5, z6, z7):
 
     a = [a0, a1, a2, a3, a4, a5, a6, a7]
     z = [z0, z1, z2, z3, z4, z5, z6, z7]
     sort = bitonicSort(a, z, ASCENDING)
+    sort.name = "sort"
     return sort
 
 
 def Array8Sorter_v(a0, a1, a2, a3, a4, a5, a6, a7,
                    z0, z1, z2, z3, z4, z5, z6, z7):
-    
+
     analyze.simulator = 'iverilog'
-    toVerilog(Array8Sorter, a0, a1, a2, a3, a4, a5, a6, a7,
-                            z0, z1, z2, z3, z4, z5, z6, z7)
-    analyze(Array8Sorter, a0, a1, a2, a3, a4, a5, a6, a7,
-                         z0, z1, z2, z3, z4, z5, z6, z7)
+    toVerilog(Array8Sorter(a0, a1, a2, a3, a4, a5, a6, a7,
+                           z0, z1, z2, z3, z4, z5, z6, z7))
+    analyze(Array8Sorter(a0, a1, a2, a3, a4, a5, a6, a7,
+                         z0, z1, z2, z3, z4, z5, z6, z7))
     # cmd = "cver -q +loadvpi=../../../cosimulation/cver/myhdl_vpi:vpi_compat_bootstrap " + \
     #      "Array8Sorter.v tb_Array8Sorter.v"
     subprocess.call("iverilog -o Array8Sorter.o Array8Sorter.v tb_Array8Sorter.v", shell=True)
     cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi Array8Sorter.o"
     return Cosimulation(cmd, **locals())
-
-

example/cookbook/bitonic/test_bitonic.py

@@ -1,18 +1,20 @@
 from random import randrange
 
+import myhdl
 from myhdl import *
 
 from bitonic import Array8Sorter, Array8Sorter_v
 
+@block
 def bench():
-    
+
     n = 8
     w = 4
-    
+
     a0, a1, a2, a3, a4, a5, a6, a7 = inputs = [Signal(intbv(0)[w:]) for i in range(n)]
     z0, z1, z2, z3, z4, z5, z6, z7 = outputs = [Signal(intbv(0)[w:]) for i in range(n)]
 
-    
+
     inst = Array8Sorter_v(a0, a1, a2, a3, a4, a5, a6, a7,
                           z0, z1, z2, z3, z4, z5, z6, z7)
 
@@ -30,11 +32,7 @@ def check():
 
 
 def test_bench():
-    sim = Simulation(bench())
-    sim.run()
+    bench().run_sim()
 
 if __name__ == '__main__':
     test_bench()
-
-
-

example/cookbook/dff/dff.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 from myhdl.conversion import analyze
 

example/cookbook/dffa/dffa.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 def dffa(q, d, clk, rst):

example/cookbook/johnson/jc2.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 ACTIVE = 0

example/cookbook/johnson/jc2_alt.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 ACTIVE = 0

example/cookbook/johnson/test_jc2.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 ACTIVE, INACTIVE = bool(0), bool(1)

example/cookbook/latch/latch.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 def latch(q, d, g):

example/cookbook/sinecomp/SineComputer.py

@@ -1,5 +1,6 @@
 from math import atan, sqrt, ceil, floor, pi
 
+import myhdl
 from myhdl import *
 
 t_State = enum("WAITING", "CALCULATING")

example/cookbook/sinecomp/test_SineComputer.py

@@ -1,6 +1,7 @@
 from math import pi, sin, cos, log
 import random
 
+import myhdl
 from myhdl import *
 
 from SineComputer import SineComputer, SineComputer_v

example/cookbook/stopwatch/StopWatch.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 from TimeCount import TimeCount

example/cookbook/stopwatch/TimeCount.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 def TimeCount(tens, ones, tenths, startstop, reset, clock):

example/cookbook/stopwatch/bcd2led.py

@@ -1,5 +1,6 @@
 import seven_segment
 
+import myhdl
 from myhdl import *
 
 code = [None] * 10

example/cookbook/stopwatch/test_TimeCount.py

@@ -1,5 +1,6 @@
 from random import randrange
 
+import myhdl
 from myhdl import *
 
 from TimeCount import TimeCount

example/cookbook/stopwatch/test_bcd2led.py

@@ -1,5 +1,6 @@
 from random import randrange
 import seven_segment
+import myhdl
 from myhdl import *
 from bcd2led import bcd2led
 

example/manual/FramerCtrl.v

@@ -1,6 +1,6 @@
 // File: FramerCtrl.v
-// Generated by MyHDL 0.8dev
-// Date: Fri Dec 21 15:02:39 2012
+// Generated by MyHDL 1.0dev
+// Date: Mon Feb 15 21:03:52 2016
 
 
 `timescale 1ns/10ps
@@ -35,7 +35,7 @@ reg [7:0] index;
 
 
 always @(posedge clk, negedge reset_n) begin: FRAMERCTRL_FSM
-    if ((reset_n == 0)) begin
+    if ((reset_n == 1'b0)) begin
         SOF <= 0;
         index <= 0;
         state <= 3'b001;
@@ -66,7 +66,7 @@ always @(posedge clk, negedge reset_n) begin: FRAMERCTRL_FSM
                         state <= 3'b001;
                     end
                 end
-                SOF <= (index == (8 - 1));
+                SOF <= ($signed({1'b0, index}) == (8 - 1));
             end
             default: begin
                 $finish;

example/manual/FramerCtrl.vhd

@@ -1,11 +1,13 @@
 -- File: FramerCtrl.vhd
--- Generated by MyHDL 0.8dev
--- Date: Fri Dec 21 15:02:39 2012
+-- Generated by MyHDL 1.0dev
+-- Date: Mon Feb 15 21:03:52 2016
 
 
 
 package pck_FramerCtrl is
 
+attribute enum_encoding: string;
+
     type t_enum_t_State_1 is (
     SEARCH,
     CONFIRM,
@@ -20,7 +22,7 @@ use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use std.textio.all;
 
-use work.pck_myhdl_08.all;
+use work.pck_myhdl_10.all;
 
 use work.pck_FramerCtrl.all;
 
@@ -43,25 +45,28 @@ end entity FramerCtrl;
 
 architecture MyHDL of FramerCtrl is
 
+
+
 signal index: unsigned(7 downto 0);
 
 begin
 
 
 
 
+
 FRAMERCTRL_FSM: process (clk, reset_n) is
 begin
     if (reset_n = '0') then
         SOF <= '0';
-        index <= "00000000";
+        index <= to_unsigned(0, 8);
         state <= SEARCH;
     elsif rising_edge(clk) then
         index <= ((index + 1) mod 8);
         SOF <= '0';
         case state is
             when SEARCH =>
-                index <= "00000001";
+                index <= to_unsigned(1, 8);
                 if bool(syncFlag) then
                     state <= CONFIRM;
                 end if;

example/manual/GrayInc.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 from bin2gray2 import bin2gray

example/manual/bin2gray2.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 def bin2gray(B, G, width):

example/manual/custom.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 def inc_comb(nextCount, count, n):

example/manual/fifo.py

@@ -1,6 +1,7 @@
 import sys
 import traceback
 
+import myhdl
 from myhdl import *
 
 class Error(Exception):