Merge pull request #87 from josyb/std_logic_ports-ShadowSignals

std_logic_ports and ShadowSignals (revisited)
myhdl · May 31, 2015 · 254e458 · 254e458
2 parents 47522fa + 06f1e20
commit 254e458
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
@@ -112,7 +112,7 @@ def __init__(self):
         self.library = "work"
         self.use_clauses = None
         self.architecture = "MyHDL"
-        self.std_logic_ports = False 
+        self.std_logic_ports = False
 
     def __call__(self, func, *args, **kwargs):
         global _converting
@@ -316,6 +316,8 @@ def _writeModuleHeader(f, intf, needPck, lib, arch, useClauses, doc, stdLogicPor
             if stdLogicPorts and s._type is intbv:
                 s._name = portname + "_num"
                 convertPort = True
+                for sl in s._slicesigs:
+                    sl._setName( 'VHDL' )
             else:
                 s._name = portname
             r = _getRangeString(s)